FPGA
Design Ideas Detailed Design Functional Simulation Synthesis & Implementation Timing Simulation Device Programming
FPGA Synthesizer
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Email: [email protected]
CIC Training Manual HDL Design Flow & Tools - 1
Course Outline
uHDL Design Flow & Tools
uHDL Coding Hints
uExplore Synopsys FPGA Express Tool
CIC Training Manual HDL Design Flow & Tools - 2
HDL Design Flow & Tools
u FPGA Design Flow
• Design Ideas
• Detailed Design
• Functional Simulation
• Synthesis & Implementation
• Timing Simulation
• Device Programming
u Altera HDL Design Flow & Tools
u Xilinx HDL Design Flow & Tools
CIC Training Manual HDL Design Flow & Tools - 3
FPGA/CPLD Design Flow
Design
Design Detailed
Detailed Functional
Functional
Ideas
Ideas Design
Design Simulation
Simulation
Device
Device Timing
Timing Synthesis &
Synthesis &
Programming
Programming Simulation
Simulation Implementation
Implementation
FPGA
CPLD t pd=22.1ns
f max=47.1MHz
CIC Training Manual HDL Design Flow & Tools - 4
Design Ideas
u What are the main design considerations?
• Design feasibility?
• Design spec?
• Cost?
• FPGA/CPLD or ASIC?
• Which FPGA/CPLD vendor?
• Which device family?
• Development time?
CIC Training Manual HDL Design Flow & Tools - 5
Detailed Design
u Choose the design entry method
• Schematic
– Gate level design
– Intuitive & easy to debug
• HDL (Hardware Description Language), e.g. Verilog & VHDL
– Descriptive & portable
– Easy to modify
• Mixed HDL & schematic
u Manage the design hierarchy
• Design partitioning
– Chip partitioning
– Logic partitioning
• Use vendor-supplied libraries or parameterized libraries to reduce design time
• Create & manage user-created libraries (circuits)
CIC Training Manual HDL Design Flow & Tools - 6
Functional Simulation
u Preparation for simulation
• Generate simulation patterns
– Waveform entry
– HDL testbench
• Generate simulation netlist
u Functional simulation
• To verify the functionality of your design only
u Simulation results
• Waveform display
• Text output
u Challenge
• Sufficient & efficient test patterns
CIC Training Manual HDL Design Flow & Tools - 7
HDL Synthesis
assign z=a&b
a
u Synthesis = Translation + Optimization
z
b
• Translate HDL design files into gate-level netlist
• Optimize according to your design constraints
– Area constraints
– Timing constraints
– Power constraints
– ...
u Main challenges
• Learn synthesizable coding style
• Write correct & synthesizable HDL design files
• Specify reasonable design constraints
• Use HDL synthesis tool efficiently
CIC Training Manual HDL Design Flow & Tools - 8
Design Implementation
a
z
b
u Implementation flow
FPGA
CPLD
01011...
• Netlist merging, flattening, data base building
• Design rule checking
• Logic optimization
• Block mapping & placement
• Net routing
• Configuration bitstream generation
u Implementation results
• Design error or warnings
• Device utilization
• Timing reports
u Challenge
• How to reach high performance & high utilization implementation?
CIC Training Manual HDL Design Flow & Tools - 9
Timing Analysis & Simulation
t pd=22.1ns
uTiming analysis
f max=47.1MHz
• Timing analysis is static, i.e., independent of input & output patterns
• To examine the timing constraints
• To show the detailed timing paths
• Can find the critical path
u Timing simulation
• To verify both the functionality & timing of the design
CIC Training Manual HDL Design Flow & Tools - 10
Device Programming
u Choose the appropriate configuration scheme FPGA
• SRAM-based FPGA/CPLD devices CPLD
– Downloading the bitstream via a download cable
– Programming onto a non-volatile memory device & attaching it on the circuit board
• OTP, EPROM, EEPROM or Flash-based FPGA/CPLD devices
– Using hardware programmer
– ISP
u Finish the board design
u Program the device
u Challenge
• Board design
• System considerations
CIC Training Manual HDL Design Flow & Tools - 11
Our Focus: HDL Design Flow
u Why HDL?
• Can express digital systems in behavior or structure domain, shortening the design time
• Can support all level of abstraction, including algorithm, RTL, gate and switch level
• Both VHDL & Verilog are formal hardware description languages, thus portable
u Typical HDL design flow
• Use VHDL or Verilog to express digital systems
– VHDL or Verilog simulation tool is required to simulate your project
• Use high-level synthesis tool to obtain structural level design
• Then use FPGA placement & routing tools to obtain physical FPGA netlist
u We assume you are familiar with VHDL or Verilog...
• In this course, we’ emphasize on FPGA HDL coding techniques for synthesis
ll
– It’ the key issue to reduce area and achieve high performance for your project
s
• We assume you know how to use VHDL or Verilog simulator too
CIC Training Manual HDL Design Flow & Tools - 12
Altera HDL Design Flow
Design Entry: Functional Simulation Design Verification
Design Entry: Design Verification
Verilog/VHDL
Verilog/VHDL (Verilog-XL/VSS)
(Verilog-XL/VSS)
Timing Simulation
HDL Synthesis
HDL Synthesis
(FPGA Compiler)
(FPGA Compiler)
Third-Party
Altera MAX+PLUS II
MAX+PLUS II
Timing Analyzer
Timing Analyzer
MAX+PLUS II
MAX+PLUS II
Compiler
Compiler Timing Analysis
Synthesis & Fitting, MAX+PLUS II
Partitioning, MAX+PLUS II
Placement, Routing Programmer
Programmer
Device Programming
CIC Training Manual HDL Design Flow & Tools - 13
Xilinx HDL Design Flow
Design Entry: Functional Simulation Design Verification
Design Entry: Design Verification
Verilog/VHDL
Verilog/VHDL (Verilog-XL/VSS)
(Verilog-XL/VSS)
Timing Simulation
Logic Synthesis
Logic Synthesis
(FPGA Compiler)
(FPGA Compiler)
Third-Party
Xilinx M1 Timing
M1 Timing
Analyzer
Analyzer
Alliance Series
Alliance Series
XACTstep M1
XACTstep M1 Timing Analysis
Optimization, Mapping, M1 Hardware
Placement & Routing M1 Hardware
Debugger
Debugger
Device Programming
CIC Training Manual HDL Design Flow & Tools - 14
Design Entry
u Write HDL design files
• Must learn synthesizable RTL Verilog or VHDL coding style for the synthesis tool
• Tool: text editor library IEEE;
use IEEE.STD_LOGIC_1164.all;
– xedit, textedit, vi, joe, ... entity converter is
port ( i3, i2, i1, i0: in STD_LOGIC;
a, b, c, d, e, f, g: out STD_LOGIC);
end converter;
module converter(i3,i2,i1,i0,a,b,c,d,e,f,g); architecture case_description of converter is
input i3, i2, i1, i0 ; begin
output a, b, c, d, e, f, g; P1: process(i3, i2, i1, i0)
reg a,b,c,d,e,f,g; variable tmp_in: STD_LOGIC_VECTOR(3 downto 0);
begin
always @(i3 or i2 or i1 or i0) begin tmp_in := i3 & i2 & i1 & i0;
case({i3,i2,i1,i0}) case tmp_in is
4'b0000: {a,b,c,d,e,f,g}=7'b1111110; when "0000" => (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) (a,b,c,d,e,f,g) HDL Functional Simulation
u Write HDL testbench files
u Prepare technology-dependent simulation model, if necessary
u Verilog functional simulation
• Tool: Verilog simulator
FCadence Verilog-XL
– Viewlogic VCS
u VHDL functional simulation
• Tool: VHDL simulator
FSynopsys VSS
– Viewlogic SpeedWave
– Cadence LeapFrog
CIC Training Manual HDL Design Flow & Tools - 16
Verilog Functional Simulation
CIC Training Manual HDL Design Flow & Tools - 17
VHDL Functional Simulation
CIC Training Manual HDL Design Flow & Tools - 18
HDL Synthesis
u Prepare synthesis library
u Transfer HDL design file into gate-level netlist
• Tool: HDL synthesis software
FSynopsys: Design Analyzer, HDL/VHDL Compiler & FPGA Compiler
– Viewlogic ViewSynthesis (for VHDL only)
– Cadence Synergy
• Generate EDIF netlist file (*.edf) for Altera design
• Generate XNF netlist files (*.sxnf) for Xilinx design
CIC Training Manual HDL Design Flow & Tools - 19
FPGA Implementation
u Gate-level netlist -> configuration bitstream & timing information
• Altera development tool: Altera MAX+PLUS II software
– MAX+PLUS II Compiler
– MAX+PLUS II Floorplan Editor
• Xilinx development tool: Xilinx XACTstep M1 software
– Xilinx Design Manager
– Flow Engine
– EPIC Design Editor
CIC Training Manual HDL Design Flow & Tools - 20
