Mainboard Intel 845 eiclient schem
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5 4 3 2 1
Intel (R) 845E Interactive
Client Reference Design
D
Revision X2 D
Last Change : 2002-09-26
# Schematic Page Prefix Netobject Changes from X1 to X2
1 COVER SHEET A_ CRITICAL ANALOG TRACES
1 All BAT54A (0-0031-1261) changed to BAT54 (0-0031-1104) due to wrong polarity
2 BLOCK DIAGRAM AC_ AC97 SIGNAL
2 R712 changed from 10k to 15k to adjust voltage
3 BLOCK-POWER APIC_ APIC SIGNAL
3 PU R756 and R757 added @ U38.15 (PG_VDDR) and U38.16 (PG_V1V5)
4 MECH-ROUTE AUD_ ANALOG AUDIO SIGNAL
4 Net on pins U3.54 and U3.55 separated (BSEL[0..1]) due to naming error
5 NOTES
5 PU R758 added at CN34.7 (SYS_RESET#)
6 CPU-P4 BUS CK_ CLOCK SIGNAL 6 PU R759 added at U39.4 (VIDPWRGD)
7 CPU-P4 POWER 7 C717 changed from 4u7 to 1u
EEn_ SERIAL EEPROM LANn
8 CPU-ITP 8 R607 not populated
EN_ ENABLE FOR POWER SOURCES
9 R571 and R572 not populated (FWH Test Pins)
9 MCH-SYSBUS & CLOCK
F_ FLOPPY DISK SIGNAL 10 R585 and R586 not populated (for LVDS 18 Bit)
10 MCH-AGP & DDR
FWH_ FIRMWARE HUB SIGNAL 11 R760 and C741 added to U7.50 to generate a V_3V3SB input delay for resume reset
11 MCH-POWER
12 R501 and R494 not populated due to PCI config of LAN 82540
C
G_ AGP BUS SIGNAL C
12 CLK-ICS950201 13 U36 FWH symbol changed due to wrong pinout (Pin 23, 24 and 25)
GND_ GND SIGNAL DERIVED
14 R496 changed to 4k7 and set to GND (PD M66EN)
13 DDR-DIMM 0 GND GND POWER
15 R525 and R499 is now populated
14 DDR-DIMM 1
H_ P4 HOSTBUS SIGNAL 16 R530 not populated due to wrong V_2V5LAN voltage
15 ICH4-SYSBUS & PCI 17 U20.G4 is now 51R Pulldown to GND
I2C_ I2C BUS SIGNAL
16 ICH4-LPC & IDE & USB 18 U20.H4 is now 33R Pullup to V_3V3LAN
IDE_ IDE SIGNAL
17 ICH4-POWER 19 AC97 Fixup (AC_SDIN0 -> Changed to AC_SDIN2 on ICH4)
INT_ INTERRUPT SIGNAL
20 Swap ICH4 Pin N20 and P21 (H_HISTB+ / H_HISTB-) due to wrong info in yellow cover
18 GLUE LOGIC
KB_ KEYBOARD SIGNAL 21 LAN 82540 Fixup (R519 populated with 0R, R517 changed to 2K49 and R513 changed to 330R)
19 SIO0-LPC47M107 22 R615 changed to 4K32 due to Cougar Bug
L_ LPC BUS SIGNAL
20 SIO1-LPC47N227 23 HW Rev changed to 2 at Glue Logic
LANn_ LAN CONTROLLER n SIGNAL
24 R373 is now populated with 10M
21 CONN-COM1/COM2/LPT LP_ LPT1284 SIGNAL
25 CN12.4 must be isolated cause of shortcut of AUD_MIC_BIAS to GND
22 CONN-COM3/COM4/KBC
M_ MEMORY BUS SIGNAL 26 PU R761-R765 added to VID[0:4]
23 AC97-AD1885 MIDI_ MIDI SIGNAL 27 PU R766 added to U23.15, PD R767 added to U23.14 (Panellink strapping options)
MS_ MOUSE SIGNAL 28 HD-LED-power connected to V_5V0 instead of V_5V0SB
24 LAN-10/100/1000 BUS
29 PD R768 added to PS_ON
25 LAN-10/100/1000 CONN P_ PCI BUS SIGNAL
30 PU R769 added to U3.28 (PGOOD408#)
B 26 VGA-COUGAR-01 SPn_ SERIAL PORT n SIGNAL 31 PD R770, R771, R772 added to power enables (default off, if CPLD not configured) B
27 VGA-COUGAR-02 32 PD R773-R776 added to serial port shut down pins
USB_ USB PORT SIGNAL
28 VGA-COUGAR-03 33 Splitted SMI# and PME# signals of SIO0 and SIO1 on ICH4-GPIOs
V_ POWER 34 Removed R383, R384, R385
29 CONN-PCI
35 Added D25 to avoid crossvoltages from VGA Monitor
ZV_ ZV VIDEO PORT SIGNAL
30 CONN-01 IDE-FLOPPY 36 Added D26 to avoid crossvoltages LPT Port
37 Alternative population of L7 to L12 with resistors (0R)
31 USB0-USB1-LAN0
38 PME# Signal of Cougar (PinB7) is set to V_3V3 via 0R
32 USB2-USB5
39 U29 (LP3965EMP) can be replaced by an 0R_1206 to power 3V3 on Cougar
33 SYSTEM CONTROL 40 Possibility to PullDown Pin D8(MD24) on Cougar to enable SDRAM
41 CN41 (JUMPER 3x1) added to connect to MPCI Pins (TIP and RING)
34 DDR-POWER
42 V_5V0 input at V_DDR supply is now controlled by XILINX CPLD (Pin 25)
35 POWER
43 Delay of PWRGOOD# (LAN 82540EM Pin A9) to enable correct EEPROM detection
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR
PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION
OR SAMPLE.
A No license, express or implied, by estoppel or otherwise, to any A
intellectual property rights is granted herein. Intel disclaims all
liability, including liability for infringement of any proprietary rights,
relating to use of information in this specification. Intel does not
warrant or represent that such use will not infringe such rights.
General Note:
Intel (R) 845E Interactive Client Reference Design
All Parts marked 'XXX1' will not be assembled in V1. THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR
All Parts marked 'XXX2' will not be assembled in V2. MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE OR THE
Title
MISUSE OF THIS INFORMATION. COVER SHEET
Size Document Number Rev
* Other names and brands may be claimed as the property of others. C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 1 of 35
5 4 3 2 1
5 4 3 2 1
Block Diagram
D D
CPU VRM CPU
Pg. 35 Clocking Glue Logic
ICS950201 Xilinx *
CK 408 Coolrunner
Pentium(R) 4 Processor
FCPGA478 Pg. 12 Pg. 18
ITP
Pg. 8 - Postcode decoding
Pg. 6, 7 - Speedstep logic
- Powerup sequencing
FSB 133MHz x4, 64b (4.3 GB/s)
1280x1024 @ 18Bit
LVDS max. 2 GB
Pg. 27
planar 845E MCH
Cougar 3DR *
DDR-DIMM
C C
i82845-E
DVI-I DVI/VGA BGA385 BGA593
16 MB int. mem. AGP 1.5V, 66MHz x4, 32b (1.1 GB/s) DDR SDRAM 2.5V, 266MHz, 64b (2.1 GB/s) DDR VR
Pg. 27
Pg. 34
I/O panel
Pg. 26, 27, 28
TV-OUT Pg. 9, 10, 11 Pg. 13
Pg. 27 PHY Pg. 14
I/O panel
i82562 Hub Interface 66MHz x4, 8b (266 MB/s)
RJ45
Pg. 31 Pg. 31
I/O panel
ICH4
PCI, 33MHz, 32b (132 MB/s) LPC 3.3V, 33MHz
B i82801 B
BGA421
SMB
5V PCI-Slot miniPCI-Slot LAN SYSMON FWH SIO SIO
Pg. 29 Pg. 29 LM87 8 Mbit LPC47N227 LPC47M107
Pg. 33 i82802AC
i82540
PLCC32
(optional Pg. 15, 16, 17 FAN
i82551/i82559)
ATA66/100
RJ45 PHOTO DIODE Pg. 33 Pg. 20 Pg. 19
Pg. 25 Pg. 24, 25
I/O panel USB2.0 AC'97
IDE0 Pg. 22 SERIAL2 SERIAL0 I/O panel Pg. 21
Pg. 30 LINE-IN I/O panel
USB AC97 Pg. 22 SERIAL3 SERIAL1 I/O panel Pg. 21
planar
LINE-OUT planar
Pg. 31, 32 AD1885 Pg. 20 FIR FDD planar Pg. 30
IDE1 HEADPHONE I/O panel
PARALLEL I/O panel Pg. 21
Pg. 30 3 * planar
MICRO I/O panel
planar K/B planar Pg. 22
A
2 * I/O panel Pg. 23 CD-ROM planar A
2 * I/O panel, powered MOUSE planar Pg. 22
2 * planar
Intel (R) 845E Interactive Client Reference Design
Title
BLOCK-DIAGRAM
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 2 of 35
5 4 3 2 1
5 4 3 2 1
SLP_S3#
ATX POWER ATX 12V
D 12V 5V 5VSB 3V3 12V D
CPU
VRM MODULE VCCP
MIC5284 VCC_1V2VID
CLK
VCC_CLK
MCH
VTT
C
ISL6225 A VCC_1V5 C
LTC1117 VCC_1V8
VCC_DDR
DIMM
ISL6225 A VCC_DDR
SLP_S4#
VCC_REF
SLP_S3# B VCC_TERM
B B
ICH4
VCC_5V0SUS
LTC1117 VCC_3V3SUS
LTC1117 VCC_1V5SUS
VCC_1V8S
VCC_1V5S
VCC_3V3S
VCC_5V0S
A A
COUGAR *
ISL6225 B V_3V3AGP
Intel (R) 845E Interactive Client Reference Design
Title
BLOCK-POWER
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 3 of 35
5 4 3 2 1
5 4 3 2 1
B1 B4 B7
BOHR4.0 BOHR4.0 BOHR4.0
Mx
Mx
Mx
M29 M10 M1
M7
B2
BOHR4.0
B5
BOHR4.0
B8
BOHR4.0 FWH B4441000.01
Mx
Mx
Mx
D D
1
2
3
4
MACADRESS BIOS IN P4_RETENT
82802AC
B3 B9 Firmware-Hub
BOHR4.0 BOHR4.0 M2
Mx
Mx
M30 BRD1 M23 M24 M25 M26
SM02/RD SM02/RD SM02/RD SM02/RD
1
2
3
4
5
6
7
8
MACADRESS PCB BGA593A/COOL
XXX1 B444B
XXX2
V_CORE V_CORE V_CORE V_CORE V_CORE
M31
M E C H
DK1 DK2 DK3 DK4 DK5 BAT_CR2032
DK204060 DK204060 DK204060 DK204060 DK204060 M11 M12
M32
HS_MCH_PIN_FIN HS_MCH_INTERFACE
V_CORE V_CORE V_CORE V_CORE V_CORE M E C H XXX1 XXX1
XXX2 XXX2
JMP_2mm54 M15 M16 M17
HS_MCH_LEVER HS_MCH_CLIP HS_MCH_PORON
DK6 DK7 DK8 DK9 DK10 XXX1 XXX1 XXX1
DK204060 DK204060 DK204060 DK204060 DK204060 XXX2 XXX2 XXX2
V_CORE V_CORE V_CORE V_CORE V_CORE
C C
DK11 DK12 DK13 DK14 DK15
DK204060 DK204060 DK204060 DK204060 DK204060
V_CORE V_CORE V_CORE
DK16 DK17 DK18
DK204060 DK204060 DK204060
MARKE1 MRKF1
MARKETOP MARKFPIT
MARKE2
MARKETOP
MARKE3
MARKETOP
B B
TP1 TP2 TP3 TP4
GND GND GND GND
A A
Intel (R) 845E Interactive Client Reference Design
Title
MECH-ROUTE
6..8,11,17,33,35 V_CORE V_CORE
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 4 of 35
5 4 3 2 1
5 4 3 2 1
INPUT DERIVED VOLTAGES --> I2C DEVICES
VOLTAGES
DEVICE ADDRESS BUS
V_12V0VRM V_12V0VRMF V_CORE V_VCCA
V_VCCIOPLL CLOCK GENERATOR 1101001x SM BUS
SO-DIMM0 1010000x SM BUS
V_12V0 V_FAN1 V_12USB2 V_12VAUD SO-DIMM1 1010001x SM BUS
V_FAN1S V_12USB2F V_AUDOUT ICH4 SLAVE 1000100x SM LINK
V_FAN1SF V_12USB2S V_5VAUD LAN CONTROLLER N/A SM LINK
D V_FAN2 V_12USB3 V_BLI LM87 HW MONITOR 0101110x SM BUS D
V_FAN2S V_12USB3F
V_FAN2SF V_12USB3S
V_5V0SB V_3V3SB V_3V3LAN V_1V5LAN
V_3V3LAN0 V_2V5LAN
PCI/AGP DEVICES
V_1V5SB
V_KB DEV IDSEL DEVICE IRQ REQ/GNT
V_KBF
00 AD16 COUGAR AGP A AGP
V_DDR V_DDRREF 01 AD17 LAN10/100/1000T G 4
02 AD18
V_USB0 V_USB0X V_DDRVTT 03 AD19
V_USB1 V_USB1X 04 AD20
V_USB2 V_USB2X 05 AD21
V_5V0 06 AD22
V_USB3 V_USB3X
V_USB4 V_USB4X 07 AD23
V_USB5 V_USB5X 08 AD24 INTERNAL LAN N/A N/A
09 AD25 MINI PCI SLOT E-F 3
10 AD26 STD PCI SLOT A-B-C-D 0
V_1V5 V_1V5A1 V_HVDD 11 AD27 RISER SLOT1 B-C-D-A 0
C
V_1V5A2 V_ICHPLL 12 AD28 C
13 AD29 RISER SLOT2 C-D-A-B 1
V_3V3AGP V_2V5_LVD V_2V5_LVD1 V_PLLVDD 14 AD30
V_LVDD1 V_2V5_LVD2 15 AD31 RISER SLOT3 D-A-B-C 2
V_LVDD2 V_CVDD
V_2V0_2V5 V_VDD1
ICH4 GPIOs
V_2V5_VDD V_VDD2
V_VDD3 GPIO DEVICE SIGNAL NAME
V_VCC1 V_DL_CL GPI6 SUPER I/O 0 SIO0_SMI#
V_AVCC1 V_DL_CLF GPI7 SUPER I/O 1 SIO1_SMI#
V_AVDD GPI8 SUPER I/O 0 SIO0_PME#
V_PVCC1 V_FPVDD
V_VREF_SII GPI12 SUPER I/O 1 SIO1_PME#
V_TVDD GPI13 CPLD XC_GPIO2
V_DBL V_VPVDD GPIO25 LAN0 KINNERETH LAN0_ENA
GPIO27 MINI PCI MPCI_ACT#
V_5DVI V_5V0CF V_AMP GPIO28 CPLD XC_GPIO1
V_PIDE V_5DVIF V_AMPIN GPIO32 PRIMARY IDE IDE_PPDIAG#
V_SIDE V_IOLAN V_AMPINX GPIO33 SECONDARY IDE IDE_SPDIAG#
B V_AMPOUT GPIO34 POWERED USB USB_PWR2ENA# B
V_FIR V_GAME
V_IR V_GAMEF V_5V0REF GPIO35 POWERED USB USB_PWR3ENA#
GPIO36 FIRMWARE HUB FWH_WP#
V_3V3 V_1V2VID GPIO37 FIRMWARE HUB FWH_TBL#
V_1V8 GPIO38 PCI RISER RISER_ID1
V_CLK GPIO39 PCI RISER RISER_ID2
GPIO40 AUDIO AMPLIFIER AMP_SHDN
V_3V3SB GPIO41 PCI RISER NOGO
GPIO42 PCI SLOT P_PRSNT1#
GPIO43 PCI SLOT P_PRSNT2#
V_RTC
V_BAT
V_RTCBIAS
V_-12V0
V_-5V0
POWER STATES
A A
ON IN STATE POWER PLANE
S5 (SOFT OFF) V_*SB, V_KB, V_*LAN, V_USB*
Intel (R) 845E Interactive Client Reference Design
S3 (SUS. TO RAM) V_DDR, V_DDRREF
Title
NOTES
S0 (FULL ON) OTHERS Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 5 of 35
5 4 3 2 1
5 4 3 2 1
H_D[0..63]
H_D[0..63] 9
U1A SW478/S1
H_A#[3..31] SPAREPIN AB1 AA24 H_D63
9 H_A#[3..31] A35# D63# H_D62
SPAREPIN Y1 AA22
SPAREPIN A34# D62# H_D61
W2 A33# D61# AA25
SPAREPIN V3 Y21 H_D60
H_A#31 A32# D60# H_D59
U4 A31# D59# Y24
H_A#30 T5 Y23 H_D58
H_A#29 A30# D58# H_D57
W1 A29# D57# W25
H_A#28 R6 Y26 H_D56
D H_A#27 A28# D56# H_D55 D
V2 A27# D55# W26
H_A#26 T4 V24 H_D54
H_A#25 A26# D54# H_D53
U3 A25# D53# V22
H_A#24 P6 U21 H_D52
H_REQ#[0..4] H_A#23 A24# D52# H_D51
9 H_REQ#[0..4] U1 A23# D51# V25
H_A#22 T2 U23 H_D50
H_A#21 A22# D50# H_D49
R3 A21# D49# U24
H_A#20 P4 U26 H_D48
H_A#19 A20# D48# H_D47
P3 A19# D47# T23
H_A#18 R2 T22 H_D46
H_A#17 A18# D46# H_D45
T1 A17# D45# T25
H_A#16 N5 T26 H_D44
H_A#15 A16# D44# H_D43
N4 A15# D43# R24
H_A#14 N2 R25 H_D42
H_A#13 A14# D42# H_D41
M1 A13# D41# P24
H_ADSTB#[0..1] H_A#12 N1 R21 H_D40
9 H_ADSTB#[0..1] H_A#11 A12# D40# H_D39
M4 A11# D39# N25
H_A#10 M3 N26 H_D38
H_A#9 A10# D38# H_D37
L2 A9# D37# M26
H_A#8 M6 N23 H_D36
H_A#7 A8# D36# H_D35
L3 A7# D35# M24
V_CORE V_CORE H_A#6 K1 P21 H_D34
H_A#5 A6# D34# H_D33
L6 A5# D33# N22
H_A#4 K4 M23 H_D32
H_A#3 A4# D32# H_D31
K2 A3# D31# H25
K23 H_D30
D30# H_D29
D29# J24
H_REQ#4 H_D28
R2
R3
R4
R5
H3 REQ4# D28# L22
H_REQ#3 J3 M21 H_D27
H_REQ#2 REQ3# D27# H_D26
J4 REQ2# D26# H24
H_REQ#1 K5 G26 H_D25
H_REQ#0 REQ1# D25# H_D24
J1 REQ0# D24# L21
H_D23
301RA
62RA
51RA
62RA
D23# D26
F26 H_D22
H_ADSTB#1 D22# H_D21
R5 ADSTB1# D21# E25
H_ADSTB#0 L5 F24 H_D20
H_ADS# ADSTB0# D20# H_D19
9 H_ADS# G1 ADS# D19# F23
C G23 H_D18 C
SPAREPIN D18# H_D17
V5 AP1# D17# E24
SPAREPIN AC1 H22 H_D16
SPAREPIN AP0# D16# H_D15
AA3 BINIT# D15# D25
IERR# AC3 J21 H_D14
SPAREPIN IERR# D14# H_D13
V6 MCERR# D13# D23
C26 H_D12
H_BR0# D12# H_D11
9 H_BR0# H6 BR0# D11# H21
G22 H_D10
H_BPRI# D10# H_D9
9 H_BPRI# D2 BPRI# D9# B25
H_BNR# G2 C24 H_D8
9 H_BNR# BNR# D8# H_D7
D7# C23
H_LOCK# G4 B24 H_D6
9 H_LOCK# LOCK# D6# H_D5
D5# D22
H_HIT# F3 C21 H_D4
9 H_HIT# H_HITM# HIT# D4# H_D3
9 H_HITM# E3 HITM# D3# A25
H_DEFER# E2 A23 H_D2
9 H_DEFER# DEFER# D2# H_D1 H_DBI#[0..3]
D1# B22 H_DBI#[0..3] 9
H_RS#[0..2] B21 H_D0
9 H_RS#[0..2] D0#
H_RS#2 F4
H_RS#1 RS2#
G5 V21 H_DBI#3
H_RS#0 RS1# DBI3#
F1 P26 H_DBI#2
SPAREPIN RS0# DBI2#
AB2 G25 H_DBI#1
H_TRDY# RSP# DBI1#
9 H_TRDY# J6 E21 H_DBI#0
TRDY# DBI0#
62RA R6 H_A20MX# C6
15 H_A20M# H_FERR# A20M# H_DBSY#
15 H_FERR# B6 FERR# DBSY# H5 H_DBSY# 9
H2 H_DRDY#
H_IGNNEX# DRDY# H_DRDY# 9
62RA R7 B2
15 H_IGNNE# H_SMIX# IGNNE#
62RA R8 B5 L25 SPAREPIN
15 H_SMI# SMI# DP3# H_DSTBN#[0..3]
K26 SPAREPIN
PWRGOOD DP2# H_DSTBN#[0..3] 9
AB23 K25 SPAREPIN
15 PWRGOOD PWRGOOD DP1#
J26 SPAREPIN
62RA R9 STPCLKY# DP0#
15 STPCLK# Y4 STPCLK#
62RA R10 CPUSLPY# AB26 H_DSTBP#[0..3]
15,18 CPUSLP# CPUSLP# H_DSTBN#3 H_DSTBP#[0..3] 9
B DSTBN3# W22 B
62RA R11 H_INTRX D1 R22 H_DSTBN#2
15 H_INTR H_NMIX LINT0 DSTBN2# H_DSTBN#1
62RA R12 E5 K22
15 H_NMI LINT1 DSTBN1# H_DSTBN#0
DSTBN0# E22 V_3V3
62RA R13 PROCHOT# C3
V_CORE PROCHOT#
W23 H_DSTBP#3 R14
CK_CPU+ DSTBP3# H_DSTBP#2 4k7A
12 CK_CPU+ AF22 BCLK0 DSTBP2# P23
CK_CPU- AF23 J23 H_DSTBP#1
12 CK_CPU- BCLK1 DSTBP1# H_DSTBP#0
DSTBP0# F21
THERMTRIP#
SPAREPIN
THERMDC
THERMDA
BSEL1 AD5
H_INIT# W5 AD6
15 H_INIT# INIT# BSEL0 BSEL0 10,12
H_CPURST# AB25 AF26 SKTOCC#
8,9 H_CPURST# RESET# SKTOCC# SKTOCC# 18
C4
B3
A2
V_CORE
THERMDC
THERMDA
R17
62RA
33 THERMDA
33 THERMDC THERMTRIP# 16
A A
SPAREPIN Intel (R) 845E Interactive Client Reference Design
7,9,11,15,16,24..27 SPAREPIN
8,12,15..17,19,20,23,26..29,33,35 V_3V3 V_3V3
4,7,8,11,17,33,35 V_CORE V_CORE Title
CPU BUS
4,7,8,10..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 6 of 35
5 4 3 2 1
5 4 3 2 1
V_CORE
R47
R18
R19
R20
R21
R22
R23
V_CORE
BPM#[0..5]
U1C SW478/S1
3x Al Electrolytic 3300uF
150RA
51RA
51RA
51RA
51RA
51RA
51RA
V_CORE V_CORE V_CORE
8 BPM#[0..5]
U1B SW478/S1 A3 VSS_0 VSS_91 P2
A9 VSS_1 VSS_92 P5 Place : Northside of P4
BPM#5 AB4 A11 P22
D BPM#4 BPM5# VSS_2 VSS_93 D
AA5 BPM4# VCC_0 A8 A13 VSS_3 VSS_94 P25
BPM#3 Y6 A10 A15 R1 + C1 + C2 + C3
BPM#2 BPM3# VCC_1 VSS_4 VSS_95
AC4 BPM2# VCC_2 A12 A17 VSS_5 VSS_96 R4
BPM#1 AB5 A14 A19 R23
BPM#0 BPM1# VCC_3 VSS_6 VSS_97 3300u/EA 3300u/EA 3300u/EA
AC6 BPM0# VCC_4 A16 A21 VSS_7 VSS_98 R26 ESR max = 12mR each
VCC_5 A18 A24 VSS_8 VSS_99 T3
VCC_6 A20 A26 VSS_9 VSS_100 T6
8,18 ITP_DBR# AE25 DBR# VCC_7 B7 B4 VSS_10 VSS_101 T21
GND GND GND
ESL max = 5nH each
VCC_8 B9 B8 VSS_11 VSS_102 T24
8 H_TCK D4 TCK VCC_9 B11 B10 VSS_12 VSS_103 U2
VCC_10 B13 B12 VSS_13 VSS_104 U5
8 H_TDI C1 TDI VCC_11 B15 B14 VSS_14 VSS_105 U22
8 H_TDO D5 TDO VCC_12 B17 B16 VSS_15 VSS_106 U25
8 H_TMS F7 TMS VCC_13 B19 B18 VSS_16 VSS_107 V1
8 H_TRST# E6 TRST# VCC_14 C8 B20 VSS_17 VSS_108 V4 V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE 9x Oscon 560uF
VCC_15 C10 B23 VSS_18 VSS_109 V23
VCC_16 C12 B26 VSS_19 VSS_110 V26 Place : Northside of P4
SPAREPIN A22 C14 C2 W3
SPAREPIN RESEVED_0 VCC_17 VSS_20 VSS_111
A7 RESEVED_1 VCC_18 C16 C5 VSS_21 VSS_112 W6
SPAREPIN AD2 C18 C7 W21 + C4 + C5 + C6 + C7 + C8 + C9 + C10 + C11 + C12
SPAREPIN AD3 RESEVED_2 VCC_19 VSS_22 VSS_113
RESEVED_3 VCC_20 C20 C9 VSS_23 VSS_114 W24
SPAREPIN AE21 D7 C11 Y2 ESR max = 9.28mR each
SPAREPIN AF3 RESEVED_4 VCC_21 VSS_24 VSS_115 680u/PA 680u/PA 680u/PA 680u/PA 680u/PA 680u/PA 680u/PA 680u/PA 680u/PA
RESEVED_5 VCC_22 D9 C13 VSS_25 VSS_116 Y5
SPAREPIN AF24 D11 C15 Y22 ESL max = 6.4nH each
SPAREPIN AF25 RESEVED_6 VCC_23 VSS_26 VSS_117
RESEVED_7 VCC_24 D13 C17 VSS_27 VSS_118 Y25
VCC_25 D15 C19 VSS_28 VSS_119 AA1
GND GND GND GND GND GND GND GND GND
Iripple = 4.080 each
VCC_26 D17 C22 VSS_29 VSS_120 AA4
SPAREPIN AC26 D19 C25 AA7
SPAREPIN AD26 ITP_CLK0 VCC_27 VSS_30 VSS_121
ITP_CLK1 VCC_28 E8 D3 VSS_31 VSS_122 AA9
VCC_29 E10 D6 VSS_32 VSS_123 AA11
1KA R24 ITP_CKO0 AA20 E12 D8 AA13
V_CORE
1KA R25 ITP_CKO1 AB22 ITPCLKOUT0 VCC_30 VSS_33 VSS_124
V_CORE ITPCLKOUT1 VCC_31 E14 D10 VSS_34 VSS_125 AA15
VCC_32 E16 D12 VSS_35 VSS_126 AA17 V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE
VCC_33 E18 D14 VSS_36 VSS_127 AA19
VCC_34 E20 D16 VSS_37 VSS_128 AA23
51RA R26 COMP0
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C41
GND L24 COMP0 VCC_35 F9 D18 VSS_38 VSS_129 AA26
51RA R27 COMP1 P1 F11 D20 AB3
GND COMP1 VCC_36 VSS_39 VSS_130
C
VCC_37 F13 D21 VSS_40 VSS_131 AB6 C
VCC_38 F15 D24 VSS_41 VSS_132 AB8
VID[0..4] F17 E1 AB10
18,33 VID[0..4] VCC_39 VSS_42 VSS_133
F19 E4 AB12
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
VCC_40 VSS_43 VSS_134
VCC_41 AA8 E7 VSS_44 VSS_135 AB14
VID4 AE1 AA10 E9 AB16
VID3 VID4 VCC_42 VSS_45 VSS_136
AE2 VID3 VCC_43 AA12 E11 VSS_46 VSS_137 AB18
VID2 AE3 AA14 E13 AB20
VID1 VID2 VCC_44 VSS_47 VSS_138 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
AE4 VID1 VCC_45 AA16 E15 VSS_48 VSS_139 AB21
VID0 AE5 AA18 E17 AB24
VID0 VCC_46 VSS_49 VSS_140
V_CORE
VCC_47 AB7 E19 VSS_50 VSS_141 AC2 14x 1206 ker Place : Northside of P4 ESR max = 3.5mR each ESL typ = 1.15nH each
VCC_48 AB9 E23 VSS_51 VSS_142 AC5
VCC_49 AB11 E26 VSS_52 VSS_143 AC7
51RA R28 TSTHI0 AD24 AB13 F2 AC9
51RA R29 TSTHI1 TESTHI0 VCC_50 VSS_53 VSS_144
AA2 TESTHI1 VCC_51 AB15 F5 VSS_54 VSS_145 AC11
51RA R30 TSTHI2 AC21 AB17 F8 AC13 V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE
TSTHI3 TESTHI2 VCC_52 VSS_55 VSS_146
51RA R31 AC20 TESTHI3 VCC_53 AB19 F10 VSS_56 VSS_147 AC15 10x 1206 ker
C27 51RA R32 TSTHI4 AC24 AC8 F12 AC17
51RA R33 TSTHI5 TESTHI4 VCC_54 VSS_57 VSS_148
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
GND AC23 TESTHI5 VCC_55 AC10 F14 VSS_58 VSS_149 AC19
VCC_56 AC12 F16 VSS_59 VSS_150 AC22 Place : Inside P4 Socket
100nA 51RA R34 TSTHI8 U6 AC14 F18 AC25
51RA R35 TSTHI9 TESTHI8 VCC_59 VSS_60 VSS_151
W4 TESTHI9 VCC_57 AC16 F22 VSS_61 VSS_152 AD1
R36 51RA R37 TSTHI10 Y3 AC18 F25 AD4
270RA TESTHI10 VCC_58 VSS_62 VSS_153
AD7 G3 AD8
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
VCC_60 VSS_63 VSS_154
VCC_61 AD9 G6 VSS_64 VSS_155 AD10 ESR max = 9.28mR each
VCC_62 AD11 G21 VSS_65 VSS_156 AD12
0RA R38 GHI# A6 AD13 G24 AD14
GND GHI#/TESTHI11 VCC_63 VSS_66 VSS_157
18 DPSLP# AD25 DPSLP#/TESTHI12 VCC_64 AD15 H1 VSS_67 VSS_158 AD16
GND GND GND GND GND GND GND GND GND GND
ESL max = 6.4nH each
VCC_65 AD17 H4 VSS_68 VSS_159 AD18
VCC_66 AD19 H23 VSS_69 VSS_160 AD21
L1 AE6 H26 AD23
V_VCCA VCC_67 VSS_70 VSS_161
AD20 VCCA VCC_68 AE8 J2 VSS_71 VSS_162 AE7
VCC_69 AE10 J5 VSS_72 VSS_163 AE9
V_VCCAX
4uH7/SB AE12 J22 AE11 V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE
+ C39 VCC_70 VSS_73 VSS_164
VCC_71 AE14 J25 VSS_74 VSS_165 AE13
VCC_72 AE16 K3 VSS_75 VSS_166 AE15
33u/TA
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
VCC_73 AE18 K6 VSS_76 VSS_167 AE17
0RA R39 AE20 K21 AE19
B V_CORE
GND_ACPU VCC_74 VSS_77 VSS_168 B
AD22 VSSA VCC_76 AF5 K24 VSS_78 VSS_169 AE22
0RA R40 AF7 L1 AE24
V_1V2VID
XXX1 VCC_77 VSS_79 VSS_170
VCC_78 AF9 L4 VSS_80 VSS_171 AE26
XXX2 C56 AF11 L23 AF1
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
VCC_79 VSS_81 VSS_172
VCC_80 AF13 L26 VSS_82 VSS_173 AF6
+ 33u/TA AF15 M2 AF8
L2 VCC_81 VSS_83 VSS_174
VCC_82 AF17 M5 VSS_84 VSS_175 AF10
V_VCCIOPLL AE23 AF19 M22 AF12
VCCIOPLL VCC_83 VSS_85 VSS_176 GND GND GND GND GND GND GND GND GND GND GND GND GND
VCC_84 AF21 M25 VSS_86 VSS_177 AF14
4uH7/SB N3 AF16
VSS_87 VSS_178
N6 VSS_88 VSS_179 AF18
V_1V2VID AF4 VCCVID VCC_75 AF2 N21 VSS_89 VSS_180 AF20 14x 1206 ker Place : Southside of P4 ESR max = 3.5mR each ESL typ = 1.15nH each
N24 VSS_90
F6 GTLREF_3
F20 GTLREF_2 VCCSENSE A5
AA6 GTLREF_1 VSSSENSE A4
AA21 GTLREF_0 GND GND V_CORE V_CORE 6x 0603 ker
to eliminate
133MHz x N
V_CORE
49R9A R41 GTLREF C59 C60 Freqs
47pA 47pA
C65 R42 C66 C67
100RA Place : Between 1206 ker
10nA 1u/CA 220pA
GND GND
GND GND GND GND
A A
35 VSSSENSE
35 VCCSENSE
SPAREPIN Intel (R) 845E Interactive Client Reference Design
6,9,11,15,16,24..27 SPAREPIN
4,6,8,11,17,33,35 V_CORE V_CORE
35 V_1V2VID V_1V2VID Title
CPU POWER
4,8,10..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 7 of 35
5 4 3 2 1
5 4 3 2 1
D D
V_CORE
V_3V3 V_3V3 V_CORE V_CORE
R731
R732
R733
R734
R735
R736
R1
R45
R46
R48
R49
BPM#[0..5]
54R9A
51RA
51RA
51RA
51RA
51RA
51RA
C C
7 BPM#[0..5]
CN1
220RA
220RA
54R9A
39RA
BPM#5 13 11
BPM#4 BPM#5 FBO
15 BPM#4
BPM#3 17 5
BPM#2 BPM#3 TCK H_TCK 7
19 BPM#2 TRST# 3 H_TRST# 7
BPM#1 21 1
BPM#0 BPM#1 TDI H_TDOITP H_TDI 7
23 7 22R6A R754
BPM#0 TDO H_TDO 7
TMS 2 H_TMS 7
6 NC2
4 NC1 DBA# 24 ITP_DBA#
DBR# 25 ITP_DBR# 7,18
V_CORE 26 VTAP
28 VTT
27 VTT GND 22
GND 20
22R6A R755 H_CPURSTX# 12 18
6,9 H_CPURST# RESET# GND
GND 16
R52
R53
12 CK_ITP+ 9 BCLK+ GND 14
12 CK_ITP- 8 BCLK- GND 10
SW28/FD
XXX1
C738
C739
XXX2
680RA
27RA
100nA
100nA
GND GND GND
GND GND
B B
A A
Intel (R) 845E Interactive Client Reference Design
6,12,15..17,19,20,23,26..29,33,35 V_3V3 V_3V3
4,6,7,11,17,33,35 V_CORE V_CORE Title
CPU-ITP
4,7,10..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 8 of 35
5 4 3 2 1
5 4 3 2 1
H_HISTB+ 15
H_HISTB- 15
H_HI[0..10]
H_HI[0..10] 15
H_HISTB+
H_HISTB-
D D
H_HI10
H_HI9
H_HI8
H_HI7
H_HI6
H_HI5
H_HI4
H_HI3
H_HI2
H_HI1
H_HI0
H_D[0..63]
H_D[0..63] 6
H_A#[3..31]
6 H_A#[3..31]
M24
M27
M25
M26
N25
N24
N28
N27
P23
P24
P25
L27
L28
H_A#31 L7 AE16 H_D63
HI_STB+
HI_STB-
HI_10
HI_9
HI_8
HI_7
HI_6
HI_5
HI_4
HI_3
HI_2
HI_1
HI_0
H_A#30 HA#31 HD#63 H_D62
M6 HA#30 HD#62 AD17
H_A#29 G2 AH17 H_D61
H_A#28 HA#29 HD#61 H_D60
N5 HA#28 HD#60 AE15
H_A#27 H4 AF16 H_D59
H_A#26 HA#27 HD#59 H_D58
L2 HA#26 HD#58 AC17
H_A#25 J3 AH15 H_D57
H_A#24 HA#25 HD#57 H_D56
H_A#23
M5 HA#24 U2A HD#56 AG17
H_D55
J2 HA#23 HD#55 AG16
H_A#22 K3 82845E AG15 H_D54
H_A#21 HA#22 HD#54 H_D53
L5 HA#21 HD#53 AE14
H_A#20 L3 AG14 H_D52
H_A#19 HA#20 HD#52 H_D51
M3 HA#19 HD#51 AF14
H_A#18 M4 AC14 H_D50
H_A#17 HA#18 HD#50 H_D49
K4 HA#17 HD#49 AH13
H_A#16 N3 AG13 H_D48
H_A#15 HA#16 HD#48 H_D47
N7 HA#15 HD#47 AF12
H_A#14 N2 AE13 H_D46
H_A#13 HA#14 HD#46 H_D45
P3 HA#13 HD#45 AG12
H_A#12 P5 AH11 H_D44
H_A#11 HA#12 HD#44 H_D43
R6 HA#11 HD#43 AG10
H_A#10 P4 AG11 H_D42
H_A#9 HA#10 HD#42 H_D41
R2 HA#9 HD#41 AF10
H_A#8 P7 AE12 H_D40
H_REQ#[0..4] H_A#7 HA#8 HD#40 H_D39
6 H_REQ#[0..4] R3 HA#7 HD#39 AC10
H_A#6 U3 AG9 H_D38
H_A#5 HA#6 HD#38 H_D37
T3 HA#5 HD#37 AD9
H_A#4 T5 AE10 H_D36
H_A#3 HA#4 HD#36 H_D35
T4 HA#3 HD#35 AC9
AE9 H_D34
HD#34 H_D33
C
HD#33 AC12 C
H_RS#[0..2] H_REQ#4 U2 AC11 H_D32
6 H_RS#[0..2] H_REQ#3 HREQ#4 HD#32 H_D31
U5 HREQ#3 HD#31 AH5
H_REQ#2 R7 AF8 H_D30
H_REQ#1 HREQ#2 HD#30 H_D29
T7 HREQ#1 HD#29 AG6
H_REQ#0 U6 AG7 H_D28
H_DBI#[0..3] HREQ#0 HD#28 H_D27
6 H_DBI#[0..3] HD#27 AG8
AF4 H_D26
H_RS#2 HD#26 H_D25
W6 RS#2 HD#25 AH3
H_RS#1 W7 AH7 H_D24
H_RS#0 RS#1 HD#24 H_D23
W2 RS#0 HD#23 AE5
AG3 H_D22
H_ADSTB#[0..1] HD#22 H_D21
6 H_ADSTB#[0..1] HD#21 AF3
H_DBI#3 AD15 AH2 H_D20
H_DBI#2 DBI#3 HD#20 H_D19
AH9 DBI#2 HD#19 AF6
H_DBI#1 AG4 AE8 H_D18
H_DBI#0 DBI#1 HD#18 H_D17
AD5 DBI#0 HD#17 AG2
AG5 H_D16
HD#16 H_D15
HD#15 AE2
H_ADSTB#1 N6 AC8 H_D14
H_ADSTB#0 HADSTB1# HD#14 H_D13
R5 HADSTB0# HD#13 AC3
H_ADS# V3 AC6 H_D12
6 H_ADS# ADS# HD#12 H_D11
HD#11 AC7
AD7 H_D10
H_TRDY# HD#10 H_D9
6 H_TRDY# U7 HTRDY# HD#9 AB7
H_DEFER# Y4 AE3 H_D8
6 H_DEFER# H_LOCK# DEFER# HD#8 H_D7
6 H_LOCK# W5 HLOCK# HD#7 AA6
AA3 H_D6
H_BPRI# HD#6 H_D5
6 H_BPRI# Y7 BPRI# HD#5 AC5
H_BR0# V7 AB4 H_D4 H_DSTBP#[0..3]
6 H_BR0# BR0# HD#4 H_D3 H_DSTBP#[0..3] 6
HD#3 AB3
H_BNR# W3 AA5 H_D2
6
H_BNR# H_DBSY# BNR# HD#2 H_D1
6 H_DBSY# V5 DBSY# HD#1 AB5
H_DRDY# V4 AA2 H_D0
6 H_DRDY# DRDY# HD#0
H_HIT# Y5
6 H_HIT# H_HITM# HIT# H_DSTBN#[0..3]
6 H_HITM# Y3 HITM# H_DSTBN#[0..3] 6
AC16 H_DSTBP#3
B HDSTBP#3 H_DSTBP#2 B
HDSTBP#2 AD11
CK_MCH66 P22 AE7 H_DSTBP#1
12 CK_MCH66 66IN HDSTBP#1 H_DSTBP#0
HDSTBP#0 AD3
CK_MCH+ J8
12 CK_MCH+ CK_MCH- BCLK+
12 CK_MCH- K8 BCLK-
AC15 H_DSTBN#3
P_RST0# HDSTBN#3 H_DSTBN#2
15,18,33 P_RST0# J27 RSTIN# HDSTBN#2 AE11
AE6 H_DSTBN#1
H_CPURST# AE17 HDSTBN#1 H_DSTBN#0
6,8 H_CPURST# CPURST# HDSTBN#0 AD4
SCK5+
SCK4+
SCK3+
SCK2+
SCK1+
SCK0+
SCK5-
SCK4-
SCK3-
SCK2-
SCK1-
SCK0-
SPAREPIN H26 TESTIN#
G15
G24
G14
G25
E24
E14
F15
J24
G6
G7
H5
F5
CK_SCK-2
CK_SCK-0
CK_SCK-1
CK_SCK-5
CK_SCK-3
CK_SCK-4
CK_SCK+2
CK_SCK+0
CK_SCK+1
CK_SCK+5
CK_SCK+3
CK_SCK+4
CK_SCK-[0..5]
CK_SCK-[0..5] 13,14
CK_SCK+[0..5]
CK_SCK+[0..5] 13,14
A A
Intel (R) 845E Interactive Client Reference Design
SPAREPIN Title
6,7,11,15,16,24..27 SPAREPIN
MCH-SYSBUS & CLOCK
4,7,8,10..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 9 of 35
5 4 3 2 1
5 4 3 2 1
G_AD[0..31] M_D[0..63]
26 G_AD[0..31] M_D[0..63] 13,14
U2B 82845E
G_AD31 AD24 G5 M_DX63 33RX4 4 3 RN1B M_D63
G_AD30 G_AD31 SDQ63 M_DX62 33RX4 RN1A M_D62
AC22 G_AD30 SDQ62 E2 2 1
G_AD29 AC24 C2 M_DX61 33RX4 4 3 RN2B M_D61
G_AD28 G_AD29 SDQ61 M_DX60 33RX4 RN2A M_D60
AC25 G_AD28 SDQ60 B2 2 1
G_AD27 AB24 F3 M_DX59 33RX4 8 7 RN1D M_D59
G_AD26 G_AD27 SDQ59 M_DX58 33RX4 RN1C M_D58
D
AA25 G_AD26 SDQ58 F4 6 5 D
G_AD25 AA24 D3 M_DX57 33RX4 8 7 RN2D M_D57
G_AD24 G_AD25 SDQ57 M_DX56 33RX4 RN2C M_D56
AB23 G_AD24 SDQ56 C3 6 5
G_AD23 Y23 E5 M_DX55 33RX4 4 3 RN3B M_D55
G_AD22 G_AD23 SDQ55 M_DX54 33RX4 RN3A M_D54
AB26 G_AD22 SDQ54 C4 2 1
G_AD21 AA27 B5 M_DX53 33RX4 8 7 RN4D M_D53
G_AD20 G_AD21 SDQ53 M_DX52 33RX4 RN4C M_D52
AB27 G_AD20 SDQ52 E6 6 5
G_AD19 AB25 B3 M_DX51 33RX4 8 7 RN3D M_D51
G_AD18 G_AD19 SDQ51 M_DX50 33RX4 RN3C M_D50
AA28 G_AD18 SDQ50 D4 6 5
G_AD17 Y26 D6 M_DX49 33RX4 4 3 RN4B M_D49
G_AD16 G_AD17 SDQ49 M_DX48 33RX4 RN4A M_D48
Y27 G_AD16 SDQ48 C6 2 1
G_AD15 V24 C7 M_DX47 33RX4 8 7 RN5D M_D47
G_AD14 G_AD15 SDQ47 M_DX46 33RX4 RN5C M_D46
U25 G_AD14 SDQ46 B7 6 5
G_AD13 U24 B9 M_DX45 33RX4 6 5 RN7C M_D45
G_AD12 G_AD13 SDQ45 M_DX44 33RX4 RN7A M_D44
T24 G_AD12 SDQ44 E11 2 1
G_AD11 U23 E8 M_DX43 33RX4 4 3 RN5B M_D43
G_AD10 G_AD11 SDQ43 M_DX42 33RX4 RN5A M_D42
T23 G_AD10 SDQ42 D8 2 1
G_AD9 V27 C9 M_DX41 33RX4 8 7 RN7D M_D41
G_AD8 G_AD9 SDQ41 M_DX40 33RX4 RN7B M_D40
V26 G_AD8 SDQ40 E10 4 3
G_AD7 U28 D10 M_DX39 33RX4 6 5 RN8C M_D39
G_AD6 G_AD7 SDQ39 M_DX38 33RX4 RN8B M_D38
U27 G_AD6 SDQ38 C11 4 3
G_AD5 T27 C13 M_DX37 33RX4 8 7 RN9D M_D37
G_C/BE#[0..3] G_AD4 G_AD5 SDQ37 M_DX36 33RX4 RN9B M_D36
26 G_C/BE#[0..3] T26 G_AD4 SDQ36 B13 4 3
G_AD3 R25 C10 M_DX35 33RX4 8 7 RN8D M_D35
G_AD2 G_AD3 SDQ35 M_DX34 33RX4 RN8A M_D34
T25 G_AD2 SDQ34 B11 2 1
G_AD1 R28 C12 M_DX33 33RX4 6 5 RN9C M_D33
G_AD0 G_AD1 SDQ33 M_DX32 33RX4 RN9A M_D32
R27 G_AD0 SDQ32 E13 2 1
G_SBA[0..7] E17 M_DX31 33RX4 8 7 RN13D M_D31
26 G_SBA[0..7] SDQ31 M_D30
C18 M_DX30 33RX4 4 3 RN13B
SDQ30 M_DX29 33RX4 RN14D M_D29
SDQ29 E19 8 7
G_C/BE#3 AA23 C20 M_DX28 33RX4 4 3 RN14B M_D28
G_C/BE#2 G_C/BE3# SDQ28 M_DX27 33RX4 RN13C M_D27
Y25 G_C/BE2# SDQ27 D18 6 5
G_ST[0..2] G_C/BE#1 V23 C19 M_DX26 33RX4 2 1 RN13A M_D26
26 G_ST[0..2] G_C/BE#0 G_C/BE1# SDQ26 M_D25
V25 D20 M_DX25 33RX4 6 5 RN14C
G_C/BE0# SDQ25 M_DX24 33RX4 RN14A M_D24
SDQ24 C21 2 1
B21 M_DX23 33RX4 8 7 RN15D M_D23
SDQ23 M_DX22 33RX4 RN15B M_D22
SDQ22 D22 4 3
G_SBA7 AE25 B23 M_DX21 33RX4 8 7 RN16D M_D21
G_SBA6 SBA7 SDQ21 M_DX20 33RX4 RN16A M_D20
C AE24 SBA6 SDQ20 C24 2 1 C
V_1V5 G_SBA5 AE27 E21 M_DX19 33RX4 6 5 RN15C M_D19
G_SBA4 SBA5 SDQ19 M_DX18 33RX4 RN15A M_D18
AE28 SBA4 SDQ18 C22 2 1
G_SBA3 AG27 E23 M_DX17 33RX4 6 5 RN16C M_D17
G_SBA2 SBA3 SDQ17 M_DX16 33RX4 RN16B M_D16
AG28 SBA2 SDQ16 D24 4 3
R106 G_SBA1 AH27 E25 M_DX15 33RX4 4 3 RN17B M_D15
1KA G_SBA0 SBA1 SDQ15 M_DX14 33RX4 RN17A M_D14
AH28 SBA0 SDQ14 D26 2 1
D27 M_DX13 33RX4 8 7 RN18D M_D13
SDQ13 M_DX12 33RX4 RN18B M_D12
R111 SDQ12 B27 4 3
G_ST1X C25 M_DX11 33RX4 8 7 RN17D M_D11
1KA SDQ11 M_D10
B25 M_DX10 33RX4 6 5 RN17C
SDQ10 M_DX9 33RX4 RN18C M_D9
3 SDQ9 C27 6 5
E27 M_DX8 33RX4 2 1 RN18A M_D8
G_ST2 SDQ8 M_DX7 33RX4 RN19C M_D7
AG26 ST2 SDQ7 B28 6 5
R117 BSELX0 1 Q1 G_ST1 AF24 F25 M_DX6 33RX4 2 1 RN19A M_D6
6,12 BSEL0 1K5A G_ST0 ST1 SDQ6 M_D5 M_SCB[0..7]
BC847/B AG25 G27 M_DX5 33RX4 6 5 RN20C
ST0 SDQ5 M_D4 M_SCB[0..7] 13,14
V_1V5 H25 M_DX4 33RX4 4 3 RN20B
R121 SDQ4 M_DX3 33RX4 RN19D M_D3
SDQ3 E28 8 7
1K5A 2 R123 R124 M_DX2 33RX4 RN19B M_D2
SDQ2 C28 4 3
2KA 2KA M_DX1 33RX4 RN20D M_D1
R128
SDQ1 F27 8 7
XXX1 G28 M_DX0 33RX4 2 1 RN20A M_D0
XXX2 SDQ0
D14 M_SCBX7 33RX4 8 7 RN10D M_SCB7
SCB7 M_SCBX6 33RX4 RN10B M_SCB6
SCB6 C15 4 3
GND GND GND GND
C17 M_SCBX5 33RX4 4 3 RN12B M_SCB5 M_SCS#[0..3]
SCB5 M_SCBX4 M_SCB4 M_SCS#[0..3] 13,14
B17 33RX4 2 1 RN12A
SCB4 M_SCBX3 M_SCB3
SET=ENABLE
6K8A
C14 33RX4 6 5 RN10C
SCB3 M_SCBX2 33RX4 RN10A M_SCB2
B15 2 1
DDR MODE SCB2
D16 M_SCBX1 33RX4 8 7 RN12D M_SCB1
SCB1 M_SCBX0 33RX4 RN12C M_SCB0
26 G_DEVSEL# W28 GDEVSEL# SCB0 C16 6 5
M_SMA[0..12]
M_SCS#1 M_SMA[0..12] 13,14
26 G_FRAME# Y24 GFRAME# SCS#3 E7
W27 F9 M_SCS#0
26 G_IRDY# GIRDY# SCS#2
W24 F7 M_SCS#3
26 G_TRDY# GTRDY# SCS#1
W23 E9 M_SCS#2
26 G_STOP# GSTOP# SCS#0
AG24 G22 M_SMAX12 0RA R138 M_SMA12
26 G_REQ# GREQ# SMA12 M_SMAX11 M_SMA11
AH25 E20 0RA R141
B 26 G_GNT# GGNT# SMA11 M_SMAX10 M_SMA10 B
F13 0RA R139
SMA10 M_SMAX9 0RA R142 M_SMA9
26 G_PAR W25 GPAR SMA9 F21
G20 M_SMAX8 0RA R144 M_SMA8
SMA8 M_SMAX7 0RA R145 M_SMA7
SMA7 G21
0RA R143 G_WBF# AE23 F19 M_SMAX6 0RA R148 M_SMA6
GND WBF# SMA6 M_SMAX5 0RA R146 M_SMA5
26 G_RBF# AE22 RBF# SMA5 E18
G19 M_SMAX4 0RA R149 M_SMA4 M_SDQS[0..8]
SMA4 M_SMAX3 M_SMA3 M_SDQS[0..8] 13,14
G18 0RA R150
SMA3 M_SMAX2 0RA R737 M_SMA2
26 G_PIPE# AF22 PIPE# SMA2 E16
F17 M_SMAX1 0RA R738 M_SMA1
SMA1 M_SMAX0 0RA R739 M_SMA0
SMA0 E12
26 G_ADSTB1+ AC27 AD_STB1+
AC28 E15 M_SDQSX8 33RA R740 M_SDQS8
26 G_ADSTB1- AD_STB1- SDQS8 M_SDQSX7 M_SDQS7
E3 33RA R741
SDQS7 M_SDQSX6 33RA R742 M_SDQS6
SDQS6 C5
R24 C8 M_SDQSX5 33RA R743 M_SDQS5
26 G_ADSTB0+ AD_STB0+ SDQS5 M_SDQSX4 M_SDQS4 M_SCKE[0..3]
R23 D12 33RA R744
26 G_ADSTB0- AD_STB0- SDQS4 M_SDQSX3 M_SDQS3 M_SCKE[0..3] 13,14
B19 33RA R147
SDQS3 M_SDQSX2 33RA R140 M_SDQS2
SDQS2 C23
AF27 C26 M_SDQSX1 33RA R137 M_SDQS1
26 G_SBSTB+ SB_STB+ SDQS1 M_SDQSX0 M_SDQS0
AF26 F26 33RA R127
26 G_SBSTB- SB_STB- SDQS0
F23 M_SCKE1
SCKE3 M_SCKE0
SCKE2 H23
40R2A R160 GRCOMP AD25 E22 M_SCKE3
GND GRCOMP SCKE1 M_SCKE2
SCKE0 G23
G13 M_SBSX1 0RA R745
RCVEN# SBS1 M_SBSX0 M_SBS1 13,14
G3 G12 0RA R746
RCVENIN# SBS0 M_SBS0 13,14
F11 M_SRASX# 0RA R747
SRAS# M_SCASX# M_SRAS# 13,14
H3 G8 0RA R748
RCVENOUT# SCAS# M_SWEX# M_SCAS# 13,14
G11 0RA R749
SWE# M_SWE# 13,14
A A
Intel (R) 845E Interactive Client Reference Design
11,17,28,33,34 V_1V5 V_1V5 Title
MCH-AGP & DDR
4,7,8,11..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 10 of 35
5 4 3 2 1
5 4 3 2 1
V_1V5 V_1V5 V_1V8
SPAREPIN
SPAREPIN
V_CORE
AG29
R161
AC29
AD21
AD23
AD27
AD26
AA22
AA26
AB21
AE26
AF23
AJ25
W22
W29
M22
N14
N16
R14
R16
U14
U16
R22
R29
U22
U26
N23
N26
P13
P15
P17
T15
L25
L29
49R9A
40R2A R162 HLRCOMP P27
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
NC2
NC1
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
V_1V8 HLRCOMP
AA21 AB11 HVREF_MCH
28 AGP_REF AGPREF HVREF1
HVREF2 AB17
V_1V5A1 T17 M7
D V_1V5 VCC1_5 HVREF3 C69 R163 D
HVREF4 R8
C70 L3 Y8 100RA
4uH7/SB + C72 HVREF5 100nA
100nA
33u/TA U2C VCCSM A5
U17 VSS VCCSM A9
GND_AMCH GND GND
82845E VCCSM A13
U13 VSS VCCSM A17
GND
VCCSM A21
C75 A25
VCCSM
VCCSM C1
L4 + 33u/TA C29
VCCSM
4uH7/SB
VCCSM D7 WIRED
V_1V5A2 T13 D11
V_1V5 VCC1_5 VCCSM V_DDR
VCCSM D15
15 HI_REF P26 HI_REF VCCSM D19
VCCSM D23
AD13 HSWNG1 VCCSM D25
301RA R164 HSWNG
C77
C78
C79
C80
C83
C84
C85
C86
V_CORE AA7 HSWNG0 VCCSM F6
VCCSM F10
24R9A R165 HRCOMP1 AC13 F14 + +
GND
24R9A R166 HRCOMP0 HRCOMP1 VCCSM
GND AC2 HRCOMP0 VCCSM F18
VCCSM F22
100nA
100nA
100nA
100nA
100nA
100nA
100u/BP
100u/BP
V_DDRREF J21 SDREF2 VCCSM G1
J9 SDREF1 VCCSM G4
VCCSM G29
30R1A R167 SMRCOMP J28 H8
V_DDRVTT SMRCOMP VCCSM
VCCSM H10
AJ23 VTT VCCSM H12
R168 C88 C89 C91 C90 AG23 H14 GND GND GND GND GND GND GND GND
150RA VTT VCCSM
AJ21 VTT VCCSM H16
10nA 10nA 100nA 100nA AG21 VTT VCCSM H18 Between All VCCSM Balls of MCH
AF20 H20
AE21
VTT VCCSM
H22
MCH and 0603 / X7R
VTT VCCSM
AD20 VTT VCCSM H24 DIMM
AB20 VTT VCCSM J5
GND GND GND GND GND
AJ19 VTT VCCSM J7
C AG19 VTT VCCSM K6 C
AE19 VTT VCCSM K22
AC19 VTT VCCSM K24
AF18 VTT VCCSM K26 V_1V5
AD18 VTT VCCSM L23
AB18 VTT
AA9 VTT
AB8 VTT
C100
C101
C92
C93
C94
C95
C96
C97
C98
C99
U8 VTT GND AA1
V_CORE M8 VTT GND AA4
AA8 + +
GND
A3 GND GND AA29
A7 GND GND AB6
100nA
100nA
100nA
100nA
100nA
100nA
A11 AB9
100u/TA
100u/TA
10u/CA
10u/CA
GND GND
C102
C103
C104
C105
C106
C109
C110
A15 GND GND AB10
A19 GND GND AB12
A23 GND GND AB13
A27 GND GND AB14
D5 GND GND AB15
GND GND GND GND GND GND GND GND GND GND
D9 AB16
10u/CA
10u/CA
GND GND
100n
100n
100n
100n
100n
D13 GND GND AB19
D17 GND GND AB22 1206 / X7R 0603 / X7R
D21 GND GND AC1
E1 GND GND AC4
E4 GND GND AC18
GND GND GND GND GND GND GND E26 AC20
GND GND
E29 GND GND AC21
F8 GND GND AC23
1206 / X7R 1206 / X5R F12 GND GND AC26
F16 GND GND AD6
F20 GND GND AD8 V_1V8
F24 GND GND AD10
G26 GND GND AD12
H9 GND GND AD14
H11 GND GND AD16
C112
C113
C114
C115
H13 GND GND AD19
H15 GND GND AD22
B
H17 GND GND AE1 B
H19 GND GND AE4
H21 GND GND AE18
100nA
100nA
100nA
J1 AE20
10u/CA
GND GND
J4 GND GND AE29
J6 GND GND AF5
J22 GND GND AF7
J26 GND GND AF9
J29 GND GND AF11
GND GND GND GND
K5 GND GND AF13
K7 GND GND AF15
K27 GND GND AF17
L1 GND GND AF19 1206 / X7R 0603 / X7R
L4 GND GND AF21
L6 GND GND AF25
L8 GND GND AG1
L22 GND GND AG18
L24 GND GND AG20
L26 GND GND AG22
M23 GND GND AH19
N1 GND GND AH21
N4 GND GND AH23
N8 GND GND AJ5
N13 GND GND AJ7
N15 GND GND AJ9
N17 GND GND AJ15
N22 GND GND AJ13
RSVD10
RSVD11
N29 AJ11
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
GND GND
P6 AJ17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
P8 GND GND AJ27
W26
G10
G16
G17
R13
R15
R17
R26
U15
U29
H27
P14
P16
V22
Y22
K25
K23
T14
T16
T22
AJ3
J23
J25
W1
W4
W8
G9
R1
R4
U1
U4
H6
H7
V6
V8
Y6
T6
T8
GND GND SPAREPIN GND
A A
SPAREPIN
6,7,9,15,16,24..27 SPAREPIN
13,14,33,34 V_DDR V_DDR
13,14,34 V_DDRREF V_DDRREF Intel (R) 845E Interactive Client Reference Design
14,34 V_DDRVTT V_DDRVTT
4,6..8,17,33,35 V_CORE V_CORE
Title
15,17,33,35 V_1V8 V_1V8 MCH-POWER
10,17,28,33,34 V_1V5 V_1V5
Size Document Number Rev
C B444B-W
4,7,8,10,12..35 GND GND 2.00
Date Friday, September 26, 2003 Sheet 11 of 35
5 4 3 2 1
5 4 3 2 1
D D
V_3V3
V_CLK
FB1
BLM21B601S
C126 C117 C118 C119 C120 C121 C122
10u/CA 100nA 100nA 100nA 100nA 100nA 100nA
U3 ICS950201GT
50 52 CK_CPUX+ R169 27RA
GND GND GND GND GND GND GND VDDCPU CPUCLK0+ CK_CPUX- CK_CPU+ 6
46 51 R170 27RA
VDDCPU CPUCLK0- CK_CPU- 6
32 VDD3V66
19 49 CK_ITPX+ R171 27RA
VDD3V66 CPUCLK1+ CK_ITPX- CK_ITP+ 8
V_3V3 14 48 R172 27RA
VDDPCI2 CPUCLK1- CK_ITP- 8
V_CLKA 8 VDDPCI1
45 CK_MCHX+ R173 27RA
CPUCLK2+ CK_MCHX- CK_MCH+ 9
FB2 37 44 R174 27RA
VDDA48 CPUCLK2- CK_MCH- 9
BLM21B601S 26 VDDA
1 VDDAREF
33 CK_MCH66X R175 33RA
3V66_0 CK_ICH66X CK_MCH66 9
C116 4 35 R176 33RA
GND 3V66_1/VCH_CLK CK_AGP66X CK_ICH66 16
C124 C125 C123 9 21 R177 33RA
GND 66M_OUT0/3V66_2 CK_RESX0 CK_RES0 CK_AGP66 26
10u/CA 15 22 R178 33RA
10nA 10nA 10nA GND 66M_OUT1/3V66_3 CK_RESX1 R179 33RA CK_RES1
V_CLK V_3V3 V_3V3 V_3V3 V_3V3 20 GND 66M_OUT2/3V66_3 23
C 31 24 CK_RESX2 R180 33RA CK_RES2 C
GND GND 66M_IN/3V66_5
36 GND
41 GND 48M_DOT 38
GND GND GND GND
47 39 CK_ICH48X R185 33RA
GND 48M_USB CK_ICH48 16
1KA
1KA
1KA
1KA
1KA
27 GNDA
5 CK_ICH33X R186 33RA
PCICLK_F0 CK_CPLDX CK_ICH33 15
R187 33RA
R181
R182
R183
R184
R769
PCICLK_F1 6 CK_CPLD 18
1KA R188 BSEL2 40 7 CK_FWHX R189 33RA
GND FS2 PCICLK_F2 CK_FWH 33
6,10 BSEL0 55 FS1
1KA R190 FS0 54 10 CK_LPC0X R191 33RA
V_CLK FS0 PCICLK0 CK_LPC1X CK_LPC0 19
11 R192 33RA
PCICLK1 CK_LANX CK_LPC1 20
53 12 R193 33RA
18 CPU_STOP# CPU_STOP# PCICLK2 CK_MPCIX CK_LAN 24
34 13 R194 33RA
18 PCI_STOP# PCI_STOP# PCICLK3 CK_SLOT1X CK_MPCI 29
25 16 R195 33RA
18 PWRDWN# PWRDN# PCICLK4 CK_SLOT2X CK_SLOT1 29
17 R196 33RA
PCICLK5 CK_SLOT3X CK_SLOT2 29
29 18 R197 33RA
13..15 SMBISOD SDATA PCICLK6 CK_SLOT3 29
13..15 SMBISOC 30 SDCLOCK
10KA R198 MULTISEL 43 56 CK_14MX R199 33RA
V_3V3
IREF_CK MULTESEL0 14MREF CK_14M 16,19,20,27
42 IREF
18 PGOOD408# 28 VTT_PWRGD#
2 XTAL_IN XTAL_OUT 3
A_CLKX1
A_CLKX2
R200 R201
1KA 475RA XT1
R15
R16
R55
R54
R56
R57
C127
C128
C129
C130
C131
C132
C133
C134
C135
C136
C137
C138
C139
C140
C141
C142
C143
14MHZ3181/QA
C144 C145
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
49R9A
49R9A
49R9A
49R9A
49R9A
49R9A
B B
10pA 10pA
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A A
Intel (R) 845E Interactive Client Reference Design
V_CLK V_CLK
6,8,15..17,19,20,23,26..29,33,35 V_3V3 V_3V3 Title
CLK ICS950201
4,7,8,10,11,13..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 12 of 35
5 4 3 2 1
5 4 3 2 1
DIMM 0
V_DDR
D D
M_SMA[0..12] M_D[0..63]
10,14 M_SMA[0..12] M_D[0..63] 10,14
104
112
128
136
143
156
164
172
180
108
120
148
168
15
22
30
54
62
77
96
38
46
70
85
7
M_SMA0 48
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
M_SMA1 A0
43 A1
M_SMA2 41 2 M_D0
M_SMA3 A2 D0 M_D1
130 A3 D1 4
M_SMA4 37 6 M_D2
M_SMA5 A4 D2 M_D3
32 A5 D3 8
M_SMA6 125 94 M_D4
M_SMA7 A6 D4 M_D5
29 A7 D5 95
M_SMA8 122 CN2 98 M_D6
M_SMA9 A8 D6 M_D7
27 A9 D7 99
M_SMA10 M_D8
M_SMA11
141 A10 SW184/D1 D8 12
M_D9
118 A11 D9 13
M_SMA12 115 19 M_D10
A12 D10 M_D11
103 A13 D11 20
105 M_D12
M_SBS0 D12 M_D13
10,14 M_SBS0 59 BA0 D13 106
M_SBS1 52 109 M_D14
10,14 M_SBS1 BA1 D14 M_D15
113 BA2 D15 110
M_SCS#[0..3] 23 M_D16
10,14 M_SCS#[0..3] D16 M_D17
163 CS3#/NC D17 24
71 28 M_D18
M_SCS#1 CS2#/NC D18 M_D19
158 CS1# D19 31
M_SCS#0 157 114 M_D20
CS0# D20 M_D21
D21 117
97 121 M_D22
DQM0 D22 M_D23
107 DQM1 D23 123
119 33 M_D24
DQM2 D24 M_D25
129 DQM3 D25 35
149 39 M_D26
GND DQM4 D26 M_D27
159 DQM5 D27 40
C 169 126 M_D28 C
DQM6 D28 M_D29
177 DQM7 D29 127
140 131 M_D30
DQM8 D30 M_D31
D31 133
M_SWE# 63 53 M_D32
10,14 M_SWE# M_SCAS# WE# D32 M_D33
10,14 M_SCAS# 65 CAS# D33 55
M_SRAS# 154 57 M_D34
10,14 M_SRAS# RAS# D34 M_D35
D35 60
M_SCKE[0..3] 146 M_D36
10,14 M_SCKE[0..3] D36 M_D37
D37 147
M_SCKE0 21 150 M_D38
CK_SCK+[0..5] M_SCKE1 CKE0 D38 M_D39
9,14 CK_SCK+[0..5] 111 CKE1 D39 151
61 M_D40
CK_SCK+0 D40 M_D41
16 CK0/DNU D41 64
CK_SCK-[0..5] CK_SCK+1 137 68 M_D42
9,14 CK_SCK-[0..5] CK1 D42 M_D43
CK_SCK+2 76 69
CK2/DNU D43 M_D44
D44 153
CK_SCK-0 17 155 M_D45
CK_SCK-1 CK0#/DNU D45 M_D46
138 CK1# D46 161
CK_SCK-2 75 162 M_D47
M_SDQS[0..8] CK2#/DNU D47 M_D48
10,14 M_SDQS[0..8] D48 72
73 M_D49
D49 M_D50
D50 79
M_SDQS0 5 80 M_D51
M_SDQS1 DQS0 D51 M_D52
14 DQS1 D52 165
M_SDQS2 25 166 M_D53
M_SDQS3 DQS2 D53 M_D54
36 DQS3 D54 170
M_SDQS4 56 171 M_D55
M_SDQS5 DQS4 D55 M_D56
67 DQS5 D56 83
M_SDQS6 78 84 M_D57
M_SDQS7 DQS6 D57 M_D58
86 DQS7 D58 87
M_SDQS8 47 88 M_D59
DQS8 D59 M_D60
D60 174
9 175 M_D61
NC1 D61 M_D62
10 NC/RESET# D62 178
101 179 M_D63
NC2 D63
102 NC3
173 44 M_SCB0
B NC4 CB0 M_SCB1 B
167 NC/FETEN CB1 45
49 M_SCB2
CB2 M_SCB3
12,14,15 SMBISOD 91 SDA CB3 51
92 134 M_SCB4
12,14,15 SMBISOC SCL CB4 M_SCB5
CB5 135
181 142 M_SCB6
SA0 CB6 M_SCB7
GND 182 SA1 CB7 144
183 SA2
WP 90
82 VDDID
184
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V_DDR VDDSPD M_SCB[0..7]
V_DDRREF 1 VREF M_SCB[0..7] 10,14
100
116
124
132
139
145
152
160
176
11
18
26
34
42
50
58
66
74
81
89
93
C146
3
100nA
GND
GND
A A
Intel (R) 845E Interactive Client Reference Design
11,14,34 V_DDRREF V_DDRREF
11,14,33,34 V_DDR V_DDR Title
DDR DIMM 0
4,7,8,10..12,14..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 13 of 35
5 4 3 2 1
5 4 3 2 1
DIMM 1
V_DDR
M_D[0..63]
M_D[0..63] 10,13
V_DDR V_DDR
M_SMA[0..12]
10,13 M_SMA[0..12]
104
112
128
136
143
156
164
172
180
108
120
148
168
15
22
30
54
62
77
96
38
46
70
85
D D
7
V_DDRVTT
M_SMA0
C147
C148
C149
C150
48
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
M_SMA1 A0
C151
C152
C153
C154
C155
C156
C157
C158
C159
C160
C161
C162
C163
C164
C165
C166
43 A1
M_SMA2 41 2 M_D0 M_D0 47RX4 2 1 RN45A
M_SMA3 A2 D0 M_D1 M_D1 47RX4 RN45D + + + +
130 A3 D1 4 8 7
M_SMA4 37 6 M_D2 M_D2 47RX4 6 5 RN44C
M_SMA5 A4 D2 M_D3 M_D3 47RX4 RN43A
32 A5 D3 8 2 1
M_SMA6 M_D4
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
125 94 M_D4 47RX4 4 3 RN45B
100u/TA
100u/TA
100u/TA
100u/TA
M_SMA7 A6 D4 M_D5 M_D5 47RX4 RN45C
29 A7 D5 95 6 5
M_SMA8 M_D6
M_SMA9
122 A8 CN3 D6 98
M_D7
M_D6
M_D7
47RX4
47RX4
4 3 RN44B
RN44D
27 A9 D7 99 8 7
M_SMA10 141 SW184/D1 12 M_D8 M_D8 47RX4 4 3 RN43B
M_SMA11 A10 D8 M_D9 M_D9 47RX4 RN43D
118 A11 D9 13 8 7
M_SMA12 115 19 M_D10 M_D10 47RX4 2 1 RN39A GND At Corner of DIMMS GND Between DIMMS
A12 D10 M_D11 M_D11 47RX4 RN39B
103 A13 D11 20 4 3
105 M_D12 M_D12 47RX4 6 5 RN43C
M_SBS0 D12 M_D13 M_D13 47RX4 RN40A
10,13 M_SBS0 59 BA0 D13 106 2 1
M_SBS1 52 109 M_D14 M_D14 47RX4 6 5 RN40C
10,13 M_SBS1 BA1 D14 M_D15
113 110 M_D15 47RX4 8 7 RN40D
M_SCS#[0..3] BA2 D15 M_D16 M_D16 47RX4 RN39D
10,13 M_SCS#[0..3] D16 23 8 7
163 24 M_D17 M_D17 47RX4 2 1 RN37A
CS3#/NC D17 M_D18 M_D18 47RX4 RN36A
71 CS2#/NC D18 28 2 1
M_SCS#3 158 31 M_D19 M_D19 47RX4 6 5 RN36C
M_SCS#2 CS1# D19 M_D20 M_D20 47RX4 RN39C
157 CS0# D20 114 6 5
117 M_D21 M_D21 47RX4 4 3 RN37B
D21 M_D22 M_D22 47RX4 RN36B
97 DQM0 D22 121 4 3
107 123 M_D23 M_D23 47RX4 8 7 RN36D
DQM1 D23 M_D24 M_D24 47RA R238
119 DQM2 D24 33 V_DDRVTT
129 35 M_D25 M_D25 47RX4 4 3 RN34B
DQM3 D25 M_D26 M_D26 47RX4 RN33A
GND 149 DQM4 D26 39 2 1
159 40 M_D27 M_D27 47RX4 6 5 RN33C
DQM5 D27 M_D28 M_D28 47RX4 RN34A
C167
C169
C170
C171
169 DQM6 D28 126 2 1
177 127 M_D29 M_D29 47RX4 6 5 RN34C V_DDRVTT
DQM7 D29 M_D30 M_D30 47RX4 RN33B
140 DQM8 D30 131 4 3
133 M_D31 M_D31 47RX4 8 7 RN33D +
M_SWE# D31 M_D32 M_D32 47RX4 RN11C
10,13 M_SWE# 63 WE# D32 53 6 5
M_SCAS# 65 55 M_D33 M_D33 47RX4 2 1 RN29A M_SMA0 56RA R750
10,13 M_SCAS# M_SRAS# CAS# D33 M_D34 M_D34 47RX4 RN29D M_SMA1 56RX4 RN32C
220u/PB
154 57 8 7 6 5
10u/CA
10u/CA
10u/CA
C C
10,13 M_SRAS# RAS# D34 M_D35
60 M_D35 47RX4 6 5 RN28C M_SMA2 56RX4 4 3 RN32B
M_SCKE[0..3] D35 M_D36 M_D36 47RX4 RN11D M_SMA3 56RX4 RN32A
10,13 M_SCKE[0..3] D36 146 8 7 2 1
147 M_D37 M_D37 47RX4 4 3 RN29B M_SMA4 56RX4 8 7 RN35D
M_SCKE2 D37 M_D38 M_D38 47RX4 RN28A M_SMA5 56RX4 RN35B
21 CKE0 D38 150 2 1 4 3
CK_SCK+[0..5] M_SCKE3 111 151 M_D39 M_D39 47RX4 4 3 RN28B M_SMA6 56RX4 6 5 RN35C
9,13 CK_SCK+[0..5] CKE1 D39 M_D40 GND
61 M_D40 47RX4 2 1 RN27A M_SMA7 56RX4 8 7 RN42D
CK_SCK+3 D40 M_D41 M_D41 47RX4 RN27C M_SMA8 56RX4 RN35A
16 CK0/DNU D41 64 6 5 2 1
CK_SCK-[0..5] CK_SCK+4 137 68 M_D42 M_D42 47RX4 4 3 RN6B M_SMA9 56RX4 6 5 RN42C
9,13 CK_SCK-[0..5] CK1 D42 M_D43
CK_SCK+5 76 69 M_D43 47RX4 6 5 RN6C M_SMA10 56RA R751
CK2/DNU D43 M_D44 M_D44 47RX4 RN28D M_SMA11 56RX4
D44 153 8 7 4 3 RN42B V_DDRVTT
CK_SCK-3 17 155 M_D45 M_D45 47RX4 4 3 RN27B M_SMA12 56RX4 2 1 RN42A
CK_SCK-4 CK0#/DNU D45 M_D46 M_D46 47RX4 RN6D
138 CK1# D46 161 8 7
CK_SCK-5 75 162 M_D47 M_D47 47RX4 2 1 RN25A M_SWE# 56RX4 6 5 RN41C
M_SDQS[0..8] CK2#/DNU D47 M_D48 M_D48 47RX4 RN25B M_SCAS# 56RX4
10,13 M_SDQS[0..8] D48 72 4 3 8 7 RN41D
M_D49 M_D49 47RX4 RN25C M_SRAS# 56RX4 3 RN41B
C172
C173
C174
C175
C176
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186
C187
C188
C189
C190
C191
D49 73 6 5 4
79 M_D50 M_D50 47RX4 2 1 RN23A
M_SDQS0 D50 M_D51 M_D51 47RX4 RN23B M_SBS0 56RX4
5 DQS0 D51 80 4 3 2 1 RN41A
M_SDQS1 14 165 M_D52 M_D52 47RX4 8 7 RN25D M_SBS1 56RA R752
M_SDQS2 DQS1 D52 M_D53 M_D53 47RX4 RN24A
25 DQS2 D53 166 2 1
M_SDQS3 M_D54 M_SCKE0
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
36 170 M_D54 47RX4 6 5 RN24C 47RX4 6 5 RN38C
M_SDQS4 DQS3 D54 M_D55 M_D55 47RX4 RN24D M_SCKE1 47RX4 RN38B
56 DQS4 D55 171 8 7 4 3
M_SDQS5 67 83 M_D56 M_D56 47RX4 2 1 RN22A M_SCKE2 47RX4 8 7 RN38D
M_SDQS6 DQS5 D56 M_D57 M_D57 47RX4 RN22B M_SCKE3 47RX4 RN38A
78 DQS6 D57 84 4 3 2 1
M_SDQS7 86 87 M_D58 M_D58 47RX4 4 3 RN21B
M_SDQS8 DQS7 D58 M_D59 M_D59 47RX4 RN21C M_SCS#0 47RX4 RN26B
47 DQS8 D59 88 6 5 4 3
174 M_D60 M_D60 47RX4 6 5 RN23C M_SCS#1 47RX4 8 7 RN26D GND
D60 M_D61 M_D61 47RX4 RN23D M_SCS#2 47RX4 RN26A
9 NC1 D61 175 8 7 2 1
10 178 M_D62 M_D62 47RX4 8 7 RN22D M_SCS#3 47RX4 6 5 RN26C
NC/RESET# D62 M_D63 M_D63 47RX4 RN21A
101 NC2 D63 179 2 1 V_DDRVTT
102 M_SDQS0 47RX4 2 1 RN44A
NC3 M_SCB0 M_SCB0 47RX4 RN31C M_SDQS1 47RX4 RN40B
173 NC4 CB0 44 6 5 4 3
167 45 M_SCB1 M_SCB1 47RX4 8 7 RN31D M_SDQS2 47RX4 6 5 RN37C
NC/FETEN CB1 M_SCB2 M_SCB2 47RX4 RN30B M_SDQS3 47RX4 RN34D
CB2 49 4 3 8 7
M_SCB3 M_SCB3 47RX4 RN30D M_SDQS4 47RX4 RN29C
C192
C193
C194
C195
C196
C197
C198
C199
C200
C201
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
12,13,15 SMBISOD 91 SDA CB3 51 8 7 6 5
92 134 M_SCB4 M_SCB4 47RX4 2 1 RN31A M_SDQS5 47RX4 2 1 RN6A
12,13,15 SMBISOC SCL CB4 M_SCB5 M_SCB5 M_SDQS6
135 47RX4 4 3 RN31B 47RX4 4 3 RN24B
CB5 M_SCB6 M_SCB6 47RX4 RN30C M_SDQS7 47RX4 RN22C
B V_DDR 181 SA0 CB6 142 6 5 6 5 B
182 144 M_SCB7 M_SCB7 47RX4 4 3 RN11B M_SDQS8 47RX4 2 1 RN30A
GND SA1 CB7
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
183 SA2
WP 90
82 VDDID
184
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V_DDR VDDSPD
V_DDRREF 1 VREF
M_SCB[0..7] GND
100
116
124
132
139
145
152
160
176
M_SCB[0..7] 10,13
11
18
26
34
42
50
58
66
74
81
89
93
C212
3
100nA V_DDRVTT
GND
GND
C213
C214
C215
C216
C217
C218
C219
C220
C221
C222
C223
C224
C225
C226
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
GND
A A
V_DDRVTT
47RX4 8 7 RN37D Intel (R) 845E Interactive Client Reference Design
56RX4 8 7 RN32D
11,34 V_DDRVTT V_DDRVTT
47RX4 8 7 RN27D
11,13,34 V_DDRREF V_DDRREF
47RX4 8 7 RN21D Title
11,13,33,34 V_DDR V_DDR
47RX4 2 1 RN11A DDR DIMM 1
4,7,8,10..13,15..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 14 of 35
5 4 3 2 1
5 4 3 2 1
V_3V3SB V_3V3
R309 R310
V_3V3SB V_3V3SB V_3V3SB V_RTC 1K5A 8K2A
SMBDATA
SMBDATA 24,29,33
R313
10KA
10KA
10KA
10KA
R311
R312
R314
V_12V0
D
24,29 P_AD[0..31]
D G D
P_AD0 H5 W6 INTRUDER#
AD0 INTRUDER# INTRUDER# 33
P_AD1 J3 AD1 U4A SMLINK0 AC3 S
P_AD2 H3 AB1 Q2
AD2 SMLINK1 SMBDATA SMBISOD
P_AD3 K1 AD3 ICH4 SM I/F SMBDATA AB4
SMBCLK
2N7002/B
SMBISOD 12..14
P_AD4 G5 AC4
P_AD5 AD4 SMBCLK SMBALERT#
J4 AD5 GPIO11/SMBALERT# AA5 SMBALERT# 24
P_AD6 H4
P_AD7 AD6
J5 AD7
P_AD8 K2
P_AD9 AD8 A20GATE
G2 AD9 A20GATE Y22 A20GATE 19
V_3V3SB V_3V3
P_AD10 L1 AB23 H_A20M#
AD10 A20M# SPAREPIN H_A20M# 6
P_AD11 G4 U23
P_AD12 AD11 DPSLP#/NC H_FERR#
L2 AD12 FERR# AA21 H_FERR# 6
P_AD13 H2 W21 H_IGNNE# R315 R316
AD13 IGNNE# H_IGNNE# 6
P_AD14 L3 V22 H_INIT# 1K5A 8K2A
AD14 INIT# H_INIT# 6
P_AD15 F5 AB22 H_INTR
AD15 INTR H_INTR 6
P_AD16 F4 AD16 CPU I/F NMI V21 H_NMI
H_NMI 6
P_AD17 N1 Y23 PWRGOOD SMBCLK
AD17 CPUPWRGD PWRGOOD 6 SMBCLK 24,29,33
P_AD18 E5 U22 KB_RST#
AD18 RCIN# KB_RST# 19
P_AD19 N2 U21 CPUSLP# V_12V0
P_AD20 AD19 CPUSLP# H_SMI#
CPUSLP# 6,18 D
E3 AD20 SMI# W23 H_SMI# 6
P_AD21 N3 V23 STPCLK#
AD21 STPCLK# STPCLK# 6 G
P_AD22 E4
P_AD23 AD22
M5 AD23 H_HI[0..10] 9 S
P_AD24 E2 Q3
P_AD25 AD24 H_HI0 2N7002/B SMBISOC
P1 AD25 HI0 L19 SMBISOC 12..14
P_AD26 E1 L20 H_HI1
P_AD27 AD26 HI1 H_HI2
P2 AD27 HI2 M19
P_AD28 D3 M21 H_HI3
P_AD29 AD28 HI3 H_HI4
R1 AD29 HI4 P19
P_AD30 D2 R19 H_HI5
P_AD31 AD30 HI5 H_HI6
P4 AD31 HI6 T20
R20 H_HI7
24,29 P_CBE#[0..3] HI7
P23 H_HI8
P_CBE#0 HI8 H_HI9
J2 C/BE0# HI9 L22
P_CBE#1 K4 Hublink I/F N22 H_HI10 V_1V8
P_CBE#2 C/BE1# HI10 SPAREPIN
M4 C/BE2# HI11 K21
C P_CBE#3 N4 C
C/BE3#
HI_STBS/HI_STB P21 H_HISTB+
H_HISTB+ 9 Hubinterface
N20 H_HISTB- R317
C1
HI_STBF/HI_STB# H_HISTB- 9
150RA reference voltages
29 P_GNT#0 GNT0# HI_COMP
29 P_GNT#1 E6 GNT1# PCI I/F HICOMP R23 R318
GND
A7 40R2A
29 P_GNT#2 GNT2#
V_3V3
29 P_GNT#3 B7 GNT3# HIREF M23 HI_REF 11
24 P_GNT#4 D6 GNT4#
SPAREPIN C5 R22
GNT5#/GNTB#/GPIO17 HI_VSWING R319 C227 C228
R320 8K2A P_REQ#0 B1 150RA
P_REQ#1 29 P_REQ#0 REQ0#
R321 8K2A A2 100nA 10nA
P_REQ#2 29 P_REQ#1 REQ1#
R322 8K2A B3 J19 APICCLK R323 0RA
P_REQ#3 29 P_REQ#2 REQ2# APICCLK
R324 8K2A C7 H19 APICD0 R325 10KA
P_REQ#4 29 P_REQ#3 REQ3# APICD0 GND
R326 8K2A B6 K20 APICD1 R327 10KA
LM87INT# 24 P_REQ#4 REQ4# APICD1
R328 8K2A A6
33 LM87INT# REQ5#/REQB#/GPIO1 GND
D5 INT_PIRQA#
PIRQA# INT_PIRQA# 26,29
C2 INT_PIRQB#
PIRQB# INT_PIRQB# 29
P5 B4 INT_PIRQC#
12 CK_ICH33 PCICLK PIRQC# INT_PIRQC# 29
A3 INT_PIRQD#
PIRQD# INT_PIRQD# 29
R329 8K2A P_DEVSEL#
24,29 P_DEVSEL# M3 DEVSEL# INT I/F GPIO2/PIRQE# C8 INT_PIRQE#
INT_PIRQE# 29
D7 INT_PIRQF#
GPIO3/PIRQF# INT_PIRQF# 29
R330 8K2A P_FRAME# F1 C3 INT_PIRQG# V_3V3
24,29 P_FRAME# FRAME# GPIO4/PIRQG# INT_PIRQG# 24
C4 INT_PIRQH#
GPIO5/PIRQH# INT_PIRQH#
R331 8K2A P_IRDY# L5
24,29 P_IRDY# IRDY#
AC13 INT_IRQ14 INT_PIRQA# R332 8K2A
IRQ14 INT_IRQ14 30
R333 8K2A P_TRDY# F2 AA19 INT_IRQ15 INT_PIRQB# R334 8K2A
24,29 P_TRDY# TRDY# IRQ15 INT_IRQ15 30
INT_PIRQC# R335 8K2A
R336 8K2A P_STOP# F3 J22 SERIRQ INT_PIRQD# R337 8K2A
24,29 P_STOP# STOP# SERIRQ SERIRQ 18..20,29
INT_PIRQE# R338 8K2A
G1 V_3V3SB INT_PIRQF# R339 8K2A
24,29 P_PAR PAR U5 V_3V3SB INT_PIRQG# R340 8K2A
R341 8K2A P_PERR# L4 D10 EE0_CS 1 8 INT_PIRQH# R342 8K2A
24,29 P_PERR# PERR# EE_CS EE0_CK CS VCC
EE_SHCLK C12 2 CK NC 7
PCIRSTX# U5 EEPROM A8 EE0_DI 3 6 EE0_8#_16 R343 INT_IRQ14 R344 8K2A
PCIRST# EE_TODIN EE0_DO DI 16/8# 10KA
D11 4 5 XXX1 C229 INT_IRQ15 R345 8K2A
R346 8K2A P_LOCK# EE_TODOUT R347 XXX1 DO GND XXX2
29 P_LOCK# M2 PLOCK# 10KA GND
SERIRQ
B
V_3V3SB R349 8K2A P_SERR# K5
B XXX2 AT93LC46-2V7
GND
100nA R348 8K2A
B
24,29 P_SERR# SERR# CK_ICHLANX
C11 R350 22RA
LAN_CLOCK CK_ICHLAN 31
R351 8K2A P_PME# W2
24,29 P_PME# PME# XC_LAN0RST# GND
V_3V3
LAN_RST# Y5 XC_LAN0RST# 18
B11 LAN_RSCX R352 22RA
8K2A P_REQA# LAN_RSTSYNC LAN_RSTSYNC 31
R353 B5
29 P_REQA# REQA#/GPIO0 LAN_XRXD0
E8 A10 R354 22RA
29 P_GNTA# GNTA#/GPIO16 LAN_RXD0 LAN_XRXD1 LAN_RXD0 31
LAN I/F LAN_RXD1 A9 R355 22RA
LAN_RXD1 31
A11 LAN_XRXD2 R356 22RA
populate for "top block swap" LAN_RXD2 LAN_RXD2 31
R357
A 8K2A
XXX1 LAN_TXD0 B10
C10
LAN_XTXD0
LAN_XTXD1
R358
R359
22RA
22RA
LAN_TXD0 31
V_3V3
LAN_TXD1 LAN_TXD1 31
XXX2 A12 LAN_XTXD2 R360 22RA
LAN_TXD2 LAN_TXD2 31
GND
V_3V3SB
U6A R361 Level Shifter for R362 R363
1 14 R364 470RA 301RA
OE# VCC XRST_SLOTS# 10KA Firmware Hub
OUT 3 P_RST_SLOTS# 29
R365 PCIRST# 2 7 INIT#
0RA IN GND 33RA
INITB#
3 FWH_INIT# 33
74LVT125
U6B GND
C230 4 14 R366 1 Q4
OE# VCC P_RSTX0# BC847/B
OUT 6 P_RST0# 9,18,33 3
10pA 5 7
XXX1 IN GND 33RA R367 2
XXX2 74LVT125 H_INIT# INITB 1 Q5
U6C BC847/B
GND R368 470RA
10 OE# VCC 14
8 P_RSTX1#
OUT P_RST1# 19,20,24,26 2
V_3V3SB 9 IN GND 7
33RA
74LVT125
U6D GND
C231 13 14 R369
OE# VCC IDE_RSTX#
A
OUT 11 IDE_RST# 30 A
100nA 12 7
IN GND 33RA
74LVT125 C232 C233 C234 C235
GND 10pA 10pA 10pA 10pA SPAREPIN
GND GND 6,7,9,11,16,24..27 SPAREPIN
XXX1 XXX1 XXX1 XXX1
XXX2 XXX2 XXX2 XXX2
11,17,33,35 V_1V8 V_1V8
GND GND GND GND Intel (R) 845E Interactive Client Reference Design
6,8,12,16,17,19,20,23,26..29,33,35 V_3V3 V_3V3
16..20,24,25,29,31..33,35 V_3V3SB V_3V3SB
16,17 V_RTC V_RTC Title
ICH4-SYSBUS & PCI
23,27,29,32..35 V_12V0 V_12V0
Size Document Number Rev
C B444B-W
4,7,8,10..14,16..35 GND GND 2.00
Date Friday, September 26, 2003 Sheet 15 of 35
5 4 3 2 1
5 4 3 2 1
V_RTC
delay RTCRST# for 10-20ms
R370
10KA
JP1
NRMRTCRST# 1
V_3V3SB 2 1-2 normal (default)
R371 CLRRTCRST# 3 2-3 clear CMOS
C236
100RA SM03/RA
1u/CA
D D
R372
8K2A GND
GND
V_RTCBIAS
R2 J23 CK_14M
19 SIO0_SMI# GPIO6/AGPBUSY# CLK14 CK_14M 12,19,20,27
18 XC_GPIO3 AC2 GPIO24/CLKRUN# U4B CLK48 F19 CK_ICH48
CK_ICH66
CK_ICH48 12
R373
CLK66 T21 CK_ICH66 12
SPAREPIN V20 NC/DPRSLPVR ICH4 10MA
CLOCK I/F RTCRST# W7 RTCRST#
AA1 XT2 C237
33 PWRBTN# PWRBTN#
AC7 RTCX1 RTCX1
RTCX1 RTCX2
GND
18,24 RI# Y1 RI# RTCX2 AC6
10pA
V_3V3SB AA6 R374
18 RSMRST# RSMRST# IDE_PDA[0..2] 30 GND
10MA
AB6 AA13 IDE_PDA0
18 PWRGD_ICH TP0 PWROK PDA0
R375 8K2A AB2 AB13 IDE_PDA1 C238
TP0/BATLOW# PDA1 IDE_PDA2 RTCX2
PDA2 W13 IDE_PDD[0..15] 30 GND
SPAREPIN W18 PM I/F
GPIO19/SLP_S1# IDE_PDD0 32KHZ768/QT 10pA
18,31,32 SLP_S3# Y4 SLP_S3# PDD0 AB11
Y2 AC11 IDE_PDD1
18 SLP_S4# SLP_S4# PDD1
AA2 Y10 IDE_PDD2
18 SLP_S5# SLP_S5# PDD2
AA10 IDE_PDD3
SPAREPIN PDD3 IDE_PDD4
T3 GPIO21/C3_STAT# PDD4 AA7
AB8 IDE_PDD5
SPAREPIN PDD5 IDE_PDD6
W19 GPIO20/STPCPU# PDD6 Y8
SPAREPIN Y21 AA8 IDE_PDD7
GPIO18/STPPCI# PDD7
Primary PDD8 AB9 IDE_PDD8
R376 33RA CK_32KSUSX AA4 Y9 IDE_PDD9 V_3V3
18,19 CK_32KSUS SUSCLK PDD9
AB3 AC9 IDE_PDD10
19,20 LPCPD# SUS_STAT#/LPCPD# PDD10
W9 IDE_PDD11
PDD11 IDE_PDD12
33 THERM# V1 THRM# PDD12 AB10
W20 W10 IDE_PDD13 R377
6 THERMTRIP# THRMTRIP# PDD13 4K7A
W11 IDE_PDD14
PDD14 IDE_PDD15
PDD15 Y11
C C
18 XC_GPIO4 J21 GPIO23/SSMUXSEL
V_3V3 AB12 IDE_PIORDY
SPAREPIN PIORDY IDE_PIORDY 30
Y20 CPUPERF#/GPIO22 Speed- PDIOR# AC12 IDE_PDIOR#
IDE_PDIOR# 30
W12 IDE_PDIOW#
step PDIOW# IDE_PDDREQ
IDE_PDIOW# 30
18 VRMPWRGD_ICH V19 VRMPWRGD/VGATE PDDREQ AA11 IDE_PDDREQ 30
R378 Y12 IDE_PDDACK#
PDDACK# IDE_PDDACK# 30
8K2A Y13 IDE_PDCS1#
PDCS1# IDE_PDCS1# 30
AB14 IDE_PDCS3#
PDCS3# IDE_PDCS3# 30
23,29 CK_ACBITCLK B8 AC_BIT_CLK IDE I/F
AC_SDOUTY
23,29 AC_RST# C13 AC_RST#
1
IDE_SDA[0..2]
XXX2 IDE_SDA[0..2] 30
short for JP2 R381 10KA AC_SDIN0X D13
V_3V3 XXX1 AC_SDIN0
SM02/RA R380 33RA AC_SDIN1X A13 AC'97 I/F AA20 IDE_SDA0
SAFE MODE XXX1
29 AC_SDIN1
R379 33RA AC_SDIN2X B13
AC_SDIN1 SDA0
AC20 IDE_SDA1
23 AC_SDIN2 AC_SDIN2 SDA1
XXX2 AC21 IDE_SDA2 IDE_SDD[0..15]
SDA2 IDE_SDD[0..15] 30
C9
2
23,29 AC_SYNC AC_SYNC
W17 IDE_SDD0
R382 33RA AC_SDOUTX SDD0 IDE_SDD1
23,29 AC_SDOUT D9 AC_SDOUT SDD1 AB17
W16 IDE_SDD2
SDD2 IDE_SDD3
18..20,33 L_AD[0..3] SDD3 AC16
W15 IDE_SDD4
L_AD0 SDD4 IDE_SDD5
T2 LAD0/FWH0 SDD5 AB15
L_AD1 R4 W14 IDE_SDD6
L_AD2 LAD1/FWH1 SDD6
T4 LAD2/FWH2 Secondary SDD7 AA14 IDE_SDD7 V_3V3
L_AD3 U2 Y14 IDE_SDD8
LAD3/FWH3 SDD8 IDE_SDD9
SDD9 AC15
18..20,33 L_FRAME# T5 LFRAME#/FWH4 LPC I/F SDD10 AA15 IDE_SDD10
Y15 IDE_SDD11
SDD11 IDE_SDD12
U3 AB16
4K7A
19 L_DRQ#0 LDRQ0# SDD12
Y16 IDE_SDD13
SDD13 IDE_SDD14
20 L_DRQ#1 U4 LDRQ1# SDD14 AA17
Y17 IDE_SDD15
SDD15
R386
C20 AC19 IDE_SIORDY
31 USB_P0+ USBP0P SIORDY IDE_SIORDY 30
D20 Y18 IDE_SDIOR#
B 31 USB_P0- USBP0N SDIOR# IDE_SDIOR# 30 B
A21 AA18 IDE_SDIOW#
31 USB_P1+ USBP1P SDIOW# IDE_SDIOW# 30
B21 AB18 IDE_SDDREQ
31 USB_P1- USBP1N SDDREQ IDE_SDDREQ 30
C18 AB19 IDE_SDDACK#
32 USB_P2+ USBP2P SDDACK# IDE_SDDACK# 30
D18 AB21 IDE_SDCS1#
32 USB_P2- USBP2N SDCS1# IDE_SDCS1# 30
A19 AC22 IDE_SDCS3#
32 USB_P3+ USBP3P SDCS3# IDE_SDCS3# 30
32 USB_P3- B19 USBP3N
32 USB_P4+ C16 USBP4P
32 USB_P4- D16 USBP4N
32 USB_P5+ A17 USBP5P USB I/F GPI7 R3 SIO1_SMI# 20
32 USB_P5- B17 USBP5N GPI8 V4 SIO0_PME# 19
GPI12 V5 SIO1_PME# 20
GPI13 W3 XC_GPIO2 18
31 USB_P0OC# B15 OC0# GPIO25 V2 LAN0_ENA 31
31 USB_P1OC# C14 OC1# GPIO27 W1 MPCI_ACT# 29
32 USB_P2OC# A15 OC2# GPIO28 W4 XC_GPIO1 18
32 USB_P3OC# B14 OC3# GPIO32 J20 IDE_PPDIAG# 30
V_3V3
32 USB_P4OC# A14 OC4# GPIO GPIO33 G22 IDE_SPDIAG# 30
32 USB_P5OC# D14 OC5# GPIO34 F20 USB_PWR2ENA# 32
GPIO35 G20 USB_PWR3ENA# 32
R387 USB_RBIAS A23 F21
GND 22RA USBRBIAS GPIO36 FWH_WP# 33
R388 USB_RBIAS# B23 H20
USBRBIAS# GPIO37 FWH_TBL# 33
C 1KA
XXX1 GPIO38 F23
H22
RISER_ID1 29
GPIO39 RISER_ID2 29
XXX2 G23
GPIO40 AMP_SHDN 23
SPKR H23 H21
23,33 SPKR SPKR GPIO41 NOGO 29
MISC GPIO42 F22 P_PRSNT1# 29
33 SYS_RESET# Y3 SYS_RESET# GPIO43 E23 P_PRSNT2# 29
A A
SPAREPIN
6,7,9,11,15,24..27 SPAREPIN
ICH4 Strapping Options
R Signal Function Default
6,8,12,15,17,19,20,23,26..29,33,35 V_3V3 V_3V3 Intel (R) 845E Interactive Client Reference Design
15,17..20,24,25,29,31..33,35 V_3V3SB V_3V3SB
A P_GNTA# top block swap NO STUFF
B EE_DOUT reserved NO STUFF 15,17 V_RTC V_RTC Title
C
JP
SPKR
AC_SDOUTX
no reboot mode
safe mode
NO STUFF
OPEN
ICH4-LPC & IDE & USB
17 V_RTCBIAS V_RTCBIAS
Size Document Number Rev
C B444B-W
4,7,8,10..15,17..35 GND GND 2.00
Date Friday, September 26, 2003 Sheet 16 of 35
5 4 3 2 1
5 4 3 2 1
V_5V0 V_3V3 V_3V3 V_5V0SB V_RTC
Battery circuitry for RTC and CMOS
C239
AB5 VCCRTC U4C VSS Y7
V_3V3SB V_RTC V_RTCBIAS
VSS Y19
R389 100nA
ICH4 VSS W8
Y6 VBIAS VSS W5
2 1KA 1 2 W22
VSS
VSS V3
D1 BAT54C E15 V17
D2 3 GND VCC5REFSUS VSS
D
3 VSS V15 D
BAT54C U20
VSS
VSS T23
C240 V_5V0REF V6 T19
1 VCC5REF VSS
E7 VCC5REF VSS T1
V_BAT 1u/CA R5
C241 C242 VSS
VSS R21
R390 R18
1u/CA 100nA VSS
1KA VSS P3
GND
V9 VCCSUS3V3 VSS P22
V8 VCCSUS3V3 VSS P20
V_3V3SB V7 VCCSUS3V3 VSS P13
GND
K14 VCCSUS3V3 VSS P11
V_RTCBIAS F18 VCCSUS3V3 VSS N5
C243
F17 VCCSUS3V3 VSS N23
V_BATX V_RTCBIASX F16 N21
R391 1KA + C244 C245 C246 C247 VCCSUS3V3 VSS
F15 VCCSUS3V3 VSS N19
47nA F10 N14
100nA 100nA 100nA VCCSUS3V3 VSS
22u/TA E11 VCCSUS3V3 VSS N13
VSS N12
BAT1
+
VSS N11
SM02/BA N10
VSS
F9 VCCLAN3V3/VCCSUS3V3 VSS M22
GND
E9 VCCLAN3V3/VCCSUS3V3 VSS M20
VSS M13
VSS M12
GND V_3V3
VSS M11
VSS M1
V18 VCC3V3 VSS L21
V16 VCC3V3 VSS L14
V10 VCC3V3 VSS L13
+ C251 + C252 C253 C254 C255 C256 C257 C258 C259 U1 L12
VCC3V3 VSS
P6 VCC3V3 VSS L11
100nA 100nA 100nA 100nA 100nA 100nA 100nA P12 L10
22u/TA 22u/TA VCC3V3 VSS
M10 VCC3V3 VSS K3
K6 VCC3V3 VSS K23
J18 VCC3V3 VSS K19
J1 VCC3V3 VSS K13
GND
C H6 VCC3V3 VSS K11 C
H18 VCC3V3 VSS J6
B2 VCC3V3 VSS H1
AC8 VCC3V3 VSS G6
V_1V8 AC17 VCC3V3 VSS G3
A5 VCC3V3 VSS G21
VSS G19
VSS F8
VSS E22
+ C265 C266 C267 E21
VSS
T22 VCCHI VSS E19
100nA 100nA P18 E18
4u7/TA VCCHI VSS
M14 VCCHI VSS E17
L23 VCCHI VSS E16
VSS E14
VSS E10
GND
VSS D22
VSS D8
V_CORE U18 VCC_CPUIO VSS D4
P14 VCC_CPUIO VSS D23
AA23 VCC_CPUIO VSS D21
VSS D19
VSS D17
+ C270 C271 D15
VSS
VSS D12
100nA D1
4u7/TA VSS
F7 VCCLAN1V5/VCCSUS1V5 VSS C6
F6 VCCLAN1V5/VCCSUS1V5 VSS C23
VSS C21
V_1V5SB
VSS C19
GND GND
VSS C17
VSS C15
U6 VCCSUS1V5 VSS B9
T6 VCCSUS1V5 VSS B22
+ C274 C275 C276 C277 R6 B20
VCCSUS1V5 VSS
G18 VCCSUS1V5 VSS B18
100nA 100nA 100nA F14 B16
22u/TA VCCSUS1V5 VSS
B
E20 VCCSUS1V5 VSS B12 B
E13 VCCSUS1V5 VSS AC5
E12 VCCSUS1V5 VSS AC23
VSS AC18
GND
VSS AC14
V_1V5
VSS AC10
VSS AC1
V14 VCC1V5 VSS AB7
U19 VCC1V5 VSS AB20
T18 VCC1V5 VSS AA9
+ C282 C284 C285 C286 P10 AA3
VCC1V5 VSS
K22 VCC1V5 VSS AA22
100nA 100nA 100nA K18 AA16
22u/TA VCC1V5 VSS
K12 VCC1V5 VSS AA12
K10 VCC1V5 VSS A4
V_1V5
VSS A22
VSS A20
GND
VSS A18
VSS A16
C22 VCCPLL VSS A1
C740 C292
10nA 100nA
GND
GND GND
A A
35 V_1V5SB V_1V5SB
10,11,28,33,34 V_1V5 V_1V5
11,15,33,35 V_1V8 V_1V8
15,16,18..20,24,25,29,31..33,35 V_3V3SB V_3V3SB
6,8,12,15,16,19,20,23,26..29,33,35 V_3V3 V_3V3
Intel (R) 845E Interactive Client Reference Design
19,21,22,31..35 V_5V0SB V_5V0SB
19..21,23,25..27,29..35 V_5V0 V_5V0
4,6..8,11,33,35 V_CORE V_CORE Title
15,16 V_RTC V_RTC INTEL ICH4 - 03
16 V_RTCBIAS V_RTCBIAS
Size Document Number Rev
C B444B-W
4,7,8,10..16,18..35 GND GND 2.00
Date Friday, September 26, 2003 Sheet 17 of 35
5 4 3 2 1
5 4 3 2 1
DPSLP# 7
V_3V3SB
3
R393
R392 DPSLP DPSLPX 1 Q6
470RA BC847/B
470RA
CPUSLP 2
D D
3 GND
R394
CPUSLPX# 1 Q7
6,15 CPUSLP#
BC847/B
470RA
2
GND
V_3V3SB
V_3V3SB R395 R396 R397 R398
10KA 10KA 10KA 10KA
V_3V3SB V_3V3SB
CN4
1 U7
C293 VCC XCTCK
3 NC1 TCK 4 62 TCK/C1 VCC1 3
5 6 XCTDO 73 18 C294 C295 C296 C297
100nA NC2 TDO XCTDI TDO/A1 VCC2
8 NC3 TDI 7 4 TDI/F1 VCC3 34
2 9 XCTMS 15 39 100nA 100nA 100nA 100nA
GND TMS R399 PORT_EN TMS/H1 VCC4
GND 10KA 11 PORT_EN/PE VCC5 51
SM09/RA 66
GND VCC6
12 CK_CPLD 87 CLK3/IN3 VCC7 82
16,19 CK_32KSUS 88 CLK2/IN2 VCC8 91
R400 XC_CK1 GND
C
V_3V3SB 10KA 89 CLK1/IN1
C
R401 XC_CK0 90
10KA CLK0/IN0
V_3V3SB
16,19,20,33 L_AD[0..3] E0 2 VRMPWRGD_ICH 16
E1 1 PWRGD_ICH 16
L_AD0 72 100
L_AD1 A2 E2 VRMOUTEN 35
71 A3 E3 99 EN_VDDR 34
R402 L_AD2 70 98
L_AD3 A4 E4 EN_V1V5 34
10KA 69 97
A5 E5 EN_1V2VID 35
16,19,20,33 L_FRAME# 68 A6 E6 96 SD_DDRVTT# 34
15,19,20,29 SERIRQ 67 A10 E12 94 XC_GPIO1 16
V_3V3SB
9,15,33 P_RST0# 65 A12 E13 93 XC_GPIO2 16
6 SKTOCC# 64 A13 E14 92 RI# 16,24
NW_MOBILE# 63 A14
7,33 VID[0..4]
R403
R404
R405
VID0 75 5
B0 F2 XC_LAN0RST# 15
1
SET = VID1 76 6
35 PWMVID[0..4] VID2 B1 F3 XC_GPIO3 16
JP3 77 7
10KA
10KA
10KA
Mobile SM02/RA VID3 78
B2 F4
8
XC_GPIO4 16
VID4 B3 F5 GND
NORTHWOOD XXX1 V_3V3SB 79 B4 F6 9 V_3V3SB HW REV 2
XXX2 PWMVID0 80 10
PWMVID1 B5 F10 GND
SW_REV2
81 12
2
PWMVID2 B6 F13 SW_REV1
83 B10 F14 13
R406 PWMVID3 84 14 SW_REV0 SW REV 0
10KA PWMVID4 B11 F15
85 B12
GND
37 CPUSLP
G1 DPSLP
20,24,29 CLKRUN# 61 C2 G2 36 V_3V3SB
0RA
0RA
0RA
60 35 7SEG0AX 7SEG0A 7
12 CPU_STOP# C3 G3 7SEG0BX 7SEG0B A
58 33 R410 150RA 6
12 PCI_STOP# C5 G4 7SEG0CX 7SEG0C B
57 32 R411 150RA 4
12 PWRDWN# C6 G5 7SEG0DX 7SEG0D C
R412 150RA
R407
R408
R409
12 PGOOD408# 56 C10 G6 31 2 D AN1 3
55 30 7SEG0EX R413 150RA 7SEG0E 1 8
16 RSMRST# C11 G10 7SEG0FX 7SEG0F E AN2
54 29 R414 150RA 10
16,31,32 SLP_S3# C12 G11 7SEG0GX 7SEG0G F
53 28 R415 150RA 9
16 SLP_S4# C13 G12 7SEG0DPX 7SEG0DP G
52 27 R416 150RA 5
16 SLP_S5# C14 G13 DP
R417 150RA U8
B B
TDSR1150
GND
7,8 ITP_DBR# 40 D1
41 16 7SEG1AX 7SEG1A 7
35 PWROK_VRM D2 H2 7SEG1BX 7SEG1B A
42 17 R418 150RA 6
35 PWROK_ATX D3 H3 7SEG1CX 7SEG1C B
44 19 R419 150RA 4
35 VIDPWRGD D4 H5 7SEG1DX 7SEG1D C
45 20 R420 150RA 2 3
34 PG_VDDR D5 H6 7SEG1EX 7SEG1E D AN1
46 21 R421 150RA 1 8
34 PG_V1V5 D6 H10 7SEG1FX 7SEG1F E AN2
47 22 R422 150RA 10
35 PS_ON D10 H11 7SEG1GX 7SEG1G F
48 23 R423 150RA 9
D11 H12 7SEG1DPX R424 150RA 7SEG1DP G
49 D12 H13 24 5 DP
R768 DELAY3V3 50 25 R425 150RA U9
10KA D13 H14 TDSR1150
GND1 26
95 GND7 GND2 38
86 GND6 GND3 43
74 GND5 GND4 59 EN_DDRSUP# 34
GND
V_3V3SB XCR3128XL
GND GND
R760
10KA
+ C741
4u7/TA
A A
GND
Intel (R) 845E Interactive Client Reference Design
15..17,19,20,24,25,29,31..33,35 V_3V3SB V_3V3SB
6,8,12,15..17,19,20,23,26..29,33,35 V_3V3 V_3V3 Title
GLUE LOGIC
4,7,8,10..17,19..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 18 of 35
5 4 3 2 1
5 4 3 2 1
V_3V3SB V_3V3
C298 + C299 C300 C301 C302 C303
100nA 100nA 100nA 100nA 100nA
4u7/TA
D D
V_3V3SB
GND GND
18
53
65
93
44
VTR
VCC
VCC
VCC
VREF
R426
10KA
12 CK_LPC0 29 PCI_CLOCK RXD1 84 SP1_RXD 21
TXD1 85 SP1_TXD 21
26 U10 89
15,20,24,26 P_RST1# PCI_RESET# DTR1# SP1_DTR# 21
DSR1# 86 SP1_DSR# 21
17 LPC47M107 87
16 SIO0_PME# IO_PME#/GPIO42 SYSOP/RTS1# SP1_RTS# 21
CTS1# 88 SP1_CTS# 21
16 L_DRQ#0 25 LDRQ# RI1# 90 SP1_RI# 21
DCD1# 91 SP1_DCD# 21
16,20 LPCPD# 27 LPCPD#
15,18,20,29 SERIRQ 30 SER_IRQ GPIO52/IRRX/RXD2 95 SP2_RXD 21
16,18,20,33 L_AD[0..3] GPIO53/IRTX/TXD2 96 SP2_TXD 21
L_AD0 20 100
LAD0 GPIO57/DTR2# SP2_DTR# 21
L_AD1 21 97
LAD1 GPIO54/DSR2# SP2_DSR# 21
L_AD2 22 98
LAD2 GPIO55/RTS2# SP2_RTS# 21
L_AD3 23 99
LAD3 GPIO56/CTS2# SP2_CTS# 21
GPIO50/RI2# 92 SP2_RI# 21
16,18,20,33 L_FRAME# 24 LFRAME# GPIO51/DCD2# 94 SP2_DCD# 21
50 62 IRTX_IR IR PORT
16 SIO0_SMI# IO_SMI#/GPIO27 GP35/IRTX2 IRRX_IR
GP34/IRRX2 61
V_5V0SB
55 CN5
27 PWM_BL FAN1/GPIO33 KEY
33 FAN1_SENSE 52 FAN_TACH1/GPIO31 1 2
54 LP_D[0..7] V_IR 3 4
33 FAN2_PWM FAN2/GPIO32 LP_D[0..7] 21
33 FAN2_SENSE 51 FAN_TACH2/GPIO30 5 6
68 LP_D0 FB5
PD0 LP_D1 BLM21B601S + C304 SM06/SA
C V_5V0
21 SP1_SD# 28 GPIO43/DDRC PD1 69 C
70 LP_D2 XXX1
PD2 LP_D3 XXX2
15 A20GATE 64 A20M/GPIO37 PD3 71 4u7/TC
63 72 LP_D4
15 KB_RST# KBDRST#/GPIO36 PD4
57 73 LP_D5
22 KB_CLK KCLOCK PD5
R427 R428 R429 R430 56 74 LP_D6
22 KB_DAT KDAT PD6 GND
75 LP_D7
PD7
22 MS_CLK 59 MCLOCK
58 IRTX_IR
22 MS_DAT MDAT
1KA 1KA 1KA 1KA 83
STB# LP_STB# 21 IRRX_IR
AFD# 82 LP_AFD# 21
J1X R431 2KA XJ1X 36 66 GND_IR
J1Y XJ1Y J1X/GPIO14 INIT# LP_INIT# 21 GND
R432 2KA 37 67
J1B1 J1Y/GPIO15 SLCTIN# LP_SLIN# 21
32 80 FB6
J1B2 J1B1/GPIO10 ACK# LP_ACK# 21
33 81 BLM21B601S
J1B2/GPIO11 ERR# LP_ERR# 21
SLCT 77 LP_SLCT 21
J2X R433 2KA XJ2X 38 79
J2Y XJ2Y J2X/GPIO16 BUSY LP_BUSY 21
R434 2KA 39 78
J2B1 J2Y/GPIO17 PE LP_PE 21
34 J2B1/GPIO12
J2B2 35 J2B2/GPIO13
33 PWR_LED_GRN 48 LED1/GPIO60 WP# 15 F_WP# 30
33 PWR_LED_YEL 49 LED2/GPIO61 INDEX# 13 F_INDEX# 30
TRAK0# 14 F_TRAK0# 30
21 SP2_SD# 41 GPIO20/P17 RDATA# 16 F_RDATA# 30
DSKCHG# 4 F_DSKCHG# 30
I/O base R435
MTR0# 3 F_MTR0# 30
address at SYSOPT0 45 43
GND GPIO24/SYSOPT GPIO22/P12/MTR1# F_MTR1# 30
0x02E DS0# 5 F_DS0# 30
4K7A 42
MIDI_INX GPIO21/P16/DS1# F_DS1# 30
MIDI_IN R436 220RA 46 8
MIDI_OUTX MIDI_IN/GPIO25 DIR# F_DIR# 30
MIDI_OUT R437 220RA 47 9
MIDI_OUT/GPIO26 STEP# F_STEP# 30
WGATE# 11 F_WGATE# 30
WDATA# 10 F_WDATA# 30
12,16,20,27 CK_14M 19 CLOCKI HDSEL# 12 F_HDSEL# 30
GPIO40/DRVDEN0 1 F_DRVDEN0 30
16,18 CK_32KSUS 6 CLOCKI32 GPIO41/DRVDEN1 2 F_DRVDEN1 30
B B
AGND
GND
GND
GND
GND
C305 C306 C307 C308 C309 C310 C311 C312
40
31
60
76
7
47pA 47pA 47pA 47pA 10nA 10nA 10nA 10nA
GND
GND
V_5V0 V_5V0
R439
R438
2KA
2KA
FB7
F1 BLM21B601S CN6
V_5V0 1 2 V_GAME V_GAMEF 1 2
J1B1 3 4 J2B2
SMD075-2 J1X 5 6 J2X
+ C313 7 8 MIDI_OUT
GND
4u7/TC 9 10 J2Y
GND
J1Y 11 12 J2B1
J1B2 13 14 MIDI_IN
A 15 16 A
SM16/WA
GND
GAME PORT/MIDI
17,20,21,23,25..27,29..35 V_5V0 V_5V0 Intel (R) 845E Interactive Client Reference Design
17,21,22,31..35 V_5V0SB V_5V0SB
15..18,20,24,25,29,31..33,35 V_3V3SB V_3V3SB
6,8,12,15..17,20,23,26..29,33,35 V_3V3 V_3V3 Title
SIO0-LPC47M107
4,7,8,10..18,20..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 19 of 35
5 4 3 2 1
5 4 3 2 1
D D
V_3V3SB V_3V3
C314 + C315 C316 C317 C318
100nA 100nA 100nA 100nA
4u7/TA
GND GND
18
53
65
93
VCCSB
VCC
VCC
VCC
12 CK_LPC1 29 PCI_CLOCK RXD1 84 SP3_RXD 22
TXD1 85 SP3_TXD 22
15,19,24,26 P_RST1# 26 PCI_RESET# DTR1# 89 SP3_DTR# 22
DSR1# 86 SP3_DSR# 22
16 SIO1_PME# 17 IO_PME# RTS1# 87 SP3_RTS# 22
U11 88
CTS1# SP3_CTS# 22
16 L_DRQ#1 25 LDRQ# RI1# 90 SP3_RI# 22
LPC47N227 91
DCD1# SP3_DCD# 22
16,19 LPCPD# 27 LPCPD#
18,24,29 CLKRUN# 28 CLKRUN#
15,18,19,29 SERIRQ 30 SER_IRQ RXD2 95 SP4_RXD 22
16,18,19,33 L_AD[0..3] TXD2 96 SP4_TXD 22
L_AD0 20 100 FB8 V_5V0
LAD0 DTR2# SP4_DTR# 22
L_AD1 21 97 BLM21B601S
LAD1 DSR2# SP4_DSR# 22 V_FIR
C L_AD2 22 98 C
LAD2 RTS2# SP4_RTS# 22
L_AD3 23 99
LAD3 CTS2# SP4_CTS# 22
RI2# 92 SP4_RI# 22
24 94 R440 R441
16,18,19,33 L_FRAME# LFRAME# DCD2# SP4_DCD# 22
100KA 100KA
I/O base address R442
SYSOPT1 49
at 0x04E V_3V3SB 10KA GPIO11/SYSOPT
61 IRRX_FIR
IRRX2 IRTX_FIR
16 SIO1_SMI# 50 GPIO12/IO_SMI# IRTX2 62
63 MODE_IRRX_FIR FIR
IRMODE/IRRX3
51 GPIO13/IRQIN1
1
CN7
2 KEY
PORT
52 GPIO14/IRQIN2 PD7 75 R443 3 4
74 IRTX1_FIR 5 6 IRRX_FIR
MTR0#/PD6 82RA
64 GPIO23/FDC_PP PD5 73
72 SM06/SA
DSKCHG#/PD4 GND
48 GPIO10 RDATA#/PD3 71
WP#/PD2 70
54 69 R444
22 SP3_SD# GPIO15 TRK0#/PD1 + C319
55 68 4K7A C320
22 SP4_SD# GPIO16 INDEX#/PD0
56 GPIO17 100nA
4u7/TC
57 GPIO20
58 GPIO21 DS0#/STB# 83
59 GPIO22 DRVDEN0#/AFD# 82
DIR#/INIT# 66
GND
6 GPIO24 STEP#/SLCTIN# 67
DS1#/ACK# 80
32 GPIO30 HDSEL#/ERR# 81
33 GPIO31 WGATE#/SLCT 77
34 GPIO32 MTR1#/BUSY 79
35 GPIO33 WRDATA#/PE 78
36 GPIO34
37 GPIO35
38 GPIO36
39 GPIO37 WP# 15
INDEX# 13
B
40 GPIO40 TRAK0# 14 B
41 GPIO41 RDATA# 16
42 GPIO42 DSKCHG# 4
43 GPIO43 MTR0# 3
44 GPIO44
45 GPIO45 DS0# 5
46 GPIO46
47 GPIO47 DIR# 8
STEP# 9
WGATE# 11
WDATA# 10
12,16,19,27 CK_14M 19 CLOCKI HDSEL# 12
DRVDEN0 1
DRVDEN1 2
GND
GND
GND
GND
31
60
76
7
GND
A A
Intel (R) 845E Interactive Client Reference Design
17,19,21,23,25..27,29..35 V_5V0 V_5V0
15..19,24,25,29,31..33,35 V_3V3SB V_3V3SB
6,8,12,15..17,19,23,26..29,33,35 V_3V3 V_3V3 Title
SIO1-LPC47N227
4,7,8,10..19,21..35 GND GND
Size Document Number Rev
C B444B-W
2.00
Date Friday, September 26, 2003 Sheet 20 of 35
5 4 3 2 1